[PATCH] D113649: [RISCV] Teach VSETVLI insertion to handle mask instruction which has avl from a PHI node.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Nov 11 00:05:28 PST 2021

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craig.topper added a comment.

I already posted a patch for this https://reviews.llvm.org/D113204


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D113649/new/

https://reviews.llvm.org/D113649

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