[PATCH] D113475: [llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets

[Zixuan Wu via Phabricator via llvm-commits]

zixuan-wu added inline comments.


================
Comment at: llvm/utils/TableGen/CompressInstEmitter.cpp:419
+  Record *Operator = SourceDag->getOperatorAsDef(Rec->getLoc());
+  if (!Operator->isSubClassOf("Inst32"))
+    PrintFatalError(Rec->getLoc(), "Input instruction '" + Operator->getName() +
----------------
craig.topper wrote:
> Are these errors the only reasons we need the Inst32 and Inst16 classes to be introduced in Target.td? Can we check the size relationships instead? If we're making this generic it doesn't seem like we should be hardcoding 16 and 32.
Hmm. Good advice. I think checking size is better way to tell the instruction width.


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  https://reviews.llvm.org/D113475/new/

https://reviews.llvm.org/D113475