[PATCH] D113376: [AArch64][SVE] Lower shuffles to permute instructions: zip1/2, uzp1/2, trn1/2
weiwei via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 8 03:40:47 PST 2021
wwei added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:19264
+ if (SDValue PermOp =
+ lowerShuffleToZIP_UZP_TRN(ShuffleMask, VT, Op1, Op2, DL, DAG))
+ return convertFromScalableVector(DAG, VT, PermOp);
----------------
david-arm wrote:
> This looks a bit wrong because VT=Fixed Length Vector Type, but Op1 and Op2 have scalable vector types.
No, the code here is correct. `VT` and `ShuffleMask` are used to check the type of the mask value, like zip or uzp mask.
`Op1` and `Op2` are used to generate new permute nodes, which will be scalable aarch64 SDNodes here.
In this patch, I encapsulated a new function for the code lowering shuffles to neon ZIP/UZP/TRN. Fortunately, the same code can be used for fixed-length SVE.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D113376/new/
https://reviews.llvm.org/D113376
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