[PATCH] D113376: [AArch64][SVE] Lower shuffles to permute instructions: zip1/2, uzp1/2, trn1/2

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:19264
+  if (SDValue PermOp =
+          lowerShuffleToZIP_UZP_TRN(ShuffleMask, VT, Op1, Op2, DL, DAG))
+    return convertFromScalableVector(DAG, VT, PermOp);
----------------
This looks a bit wrong because VT=Fixed Length Vector Type, but Op1 and Op2 have scalable vector types. 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113376/new/

https://reviews.llvm.org/D113376