[PATCH] D111117: [RISCV] Optimize (add (shl x, c0), c1)

[Ben Shi via Phabricator via llvm-commits]

benshi001 abandoned this revision.
benshi001 added a comment.

In D111117#3111631 <https://reviews.llvm.org/D111117#3111631>, @asb wrote:

> I'm seeing some code size regressions on this patch - specifically, cases where a reg-reg add is replaced with an addi -256 (which isn't compressible). e.g. 20050121-1.c from the GCC torture suite (-O1, rv32imafdc).

Thanks for your patient and careful test, I will made a new patch for SHL related optimization after a careful check.


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