[PATCH] D106237: [ISel] Port AArch64 HADD and RHADD to ISel

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

I haven't had a change to look at it recently - I've been busy with other things. I hope to get back to this at some point - it would be good to share it between backends.



================
Comment at: llvm/include/llvm/CodeGen/ISDOpcodes.h:614
 
+  /// HADDS/HADDU - Having add - Add two integers using an integer of type
+  /// i[N+1], halving the result by shifting it one bit right.
----------------
craig.topper wrote:
> efriedma wrote:
> > RKSimon wrote:
> > > having add?
> > > Maybe add a code snippet?
> > There's really very little incentive to keep ISD opcode names short, particularly rarely used ones like this.  I'd prefer to spell it out (particularly the "h"; for example, x86 has "haddps", where the "h" stands for "horizontal").
> > 
> > Maybe ADD_HALVE_UNSIGNED_ROUND_DOWN and ADD_HALVE_SIGNED_ROUND_UP?
> Halide calls these halving_add and rounding_halving_add.
I'll be honest - I didn't much like the sound of ADD_HALVE_UNSIGNED_ROUND_DOWN. I'm not a fan of how long that name is. Arm uses the name HADD, with S/U or V before it. X86 uses AVG and RISCV uses AAVG I believe, if I was looking up the right instruction. I'm not sure if they have the same concepts of rounding RHADD though, which rounds up. I think gcc calls them AVG_FLOOR and AVG_CEIL.

Any of those names or HALVING_ADD would be find by me.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106237/new/

https://reviews.llvm.org/D106237