[PATCH] D106237: [ISel] Port AArch64 HADD and RHADD to ISel

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Instead of making this part of SimplifyDemandedBits, could you emit (and (sext (hadds X, Y)), 0x7fffffff) for the (lshr (add (sext(X), sext(Y)), 1) case and let the AND be optimized by itself? Or would the transform not be profitable if it doesn't get removed?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106237/new/

https://reviews.llvm.org/D106237