[PATCH] D112917: [AMDGPU] Shrink v_mac_legacy_f32 and v_fmac_legacy_f32

[Jay Foad via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2b548b18c110: [AMDGPU] Shrink v_mac_legacy_f32 and v_fmac_legacy_f32 (authored by foad).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112917/new/

https://reviews.llvm.org/D112917

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll


Index: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll
+++ llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll
@@ -51,7 +51,7 @@
 }
 
 ; GCN-LABEL: {{^}}test_mad_legacy_f32:
-; GFX6: v_mac_legacy_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
+; GFX6: v_mac_legacy_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
 ; GFX8: v_mad_legacy_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
 ; GFX9: v_mad_legacy_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
 ; GFX101: v_mac_legacy_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
Index: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
+++ llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
@@ -7,7 +7,7 @@
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
-; GCN-NEXT:    v_fmac_legacy_f32_e64 v2, v0, v1
+; GCN-NEXT:    v_fmac_legacy_f32_e32 v2, v0, v1
 ; GCN-NEXT:    v_mov_b32_e32 v0, v2
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %fma = call float @llvm.amdgcn.fma.legacy(float %a, float %b, float %c)
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
@@ -272,7 +272,7 @@
 ; GFX6-LABEL: v_mad_legacy_f32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_mac_legacy_f32_e64 v2, v0, v1
+; GFX6-NEXT:    v_mac_legacy_f32_e32 v2, v0, v1
 ; GFX6-NEXT:    v_mov_b32_e32 v0, v2
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -292,7 +292,7 @@
 ; GFX101:       ; %bb.0:
 ; GFX101-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX101-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX101-NEXT:    v_mac_legacy_f32_e64 v2, v0, v1
+; GFX101-NEXT:    v_mac_legacy_f32_e32 v2, v0, v1
 ; GFX101-NEXT:    v_mov_b32_e32 v0, v2
 ; GFX101-NEXT:    s_setpc_b64 s[30:31]
 ;
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3597,11 +3597,13 @@
         // Additional verification is needed for sdst/src2.
         return true;
       }
-      case AMDGPU::V_MAC_F32_e64:
       case AMDGPU::V_MAC_F16_e64:
-      case AMDGPU::V_FMAC_F32_e64:
+      case AMDGPU::V_MAC_F32_e64:
+      case AMDGPU::V_MAC_LEGACY_F32_e64:
       case AMDGPU::V_FMAC_F16_e64:
+      case AMDGPU::V_FMAC_F32_e64:
       case AMDGPU::V_FMAC_F64_e64:
+      case AMDGPU::V_FMAC_LEGACY_F32_e64:
         if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) ||
             hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))
           return false;


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