[PATCH] D112692: [RISCV] Generate pseudo instruction li

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:708
 
+def : InstAlias<"li $rd, $imm",  (ADDI GPR:$rd, X0,  simm12:$imm)>;
 def : InstAlias<"mv $rd, $rs",   (ADDI GPR:$rd, GPR:$rs,       0)>;
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Either don't bother trying to align it or add spaces to the ones below so it can be properly aligned; currently it looks weird


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112692/new/

https://reviews.llvm.org/D112692