[PATCH] D112692: [RISCV] Generate pseudo instruction li

wangpc via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 28 02:37:12 PDT 2021 

pcwang-thead updated this revision to Diff 382961.
pcwang-thead added a comment.

Fix errors in `llvm\test\MC\RISCV\rv64zbs-aliases-valid.s` and `llvm\test\MC\RISCV\rv64zba-aliases-valid.s`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112692/new/

https://reviews.llvm.org/D112692

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/addimm-mulimm.ll
  llvm/test/CodeGen/RISCV/alloca.ll
  llvm/test/CodeGen/RISCV/alu32.ll
  llvm/test/CodeGen/RISCV/alu64.ll
  llvm/test/CodeGen/RISCV/analyze-branch.ll
  llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
  llvm/test/CodeGen/RISCV/atomic-load-store.ll
  llvm/test/CodeGen/RISCV/atomic-rmw.ll
  llvm/test/CodeGen/RISCV/atomic-signext.ll
  llvm/test/CodeGen/RISCV/branch-relaxation.ll
  llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
  llvm/test/CodeGen/RISCV/calling-conv-half.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
  llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
  llvm/test/CodeGen/RISCV/codemodel-lowering.ll
  llvm/test/CodeGen/RISCV/copysign-casts.ll
  llvm/test/CodeGen/RISCV/div.ll
  llvm/test/CodeGen/RISCV/double-arith.ll
  llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/double-br-fcmp.ll
  llvm/test/CodeGen/RISCV/double-calling-conv.ll
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/double-fcmp.ll
  llvm/test/CodeGen/RISCV/double-intrinsics.ll
  llvm/test/CodeGen/RISCV/double-previous-failure.ll
  llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
  llvm/test/CodeGen/RISCV/float-br-fcmp.ll
  llvm/test/CodeGen/RISCV/float-convert.ll
  llvm/test/CodeGen/RISCV/float-fcmp.ll
  llvm/test/CodeGen/RISCV/flt-rounds.ll
  llvm/test/CodeGen/RISCV/fp-imm.ll
  llvm/test/CodeGen/RISCV/frame.ll
  llvm/test/CodeGen/RISCV/half-br-fcmp.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/half-fcmp.ll
  llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
  llvm/test/CodeGen/RISCV/i32-icmp.ll
  llvm/test/CodeGen/RISCV/imm.ll
  llvm/test/CodeGen/RISCV/indirectbr.ll
  llvm/test/CodeGen/RISCV/jumptable.ll
  llvm/test/CodeGen/RISCV/legalize-fneg.ll
  llvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
  llvm/test/CodeGen/RISCV/mul.ll
  llvm/test/CodeGen/RISCV/pr51206.ll
  llvm/test/CodeGen/RISCV/rem.ll
  llvm/test/CodeGen/RISCV/remat.ll
  llvm/test/CodeGen/RISCV/rotl-rotr.ll
  llvm/test/CodeGen/RISCV/rv32zba.ll
  llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
  llvm/test/CodeGen/RISCV/rv32zbb.ll
  llvm/test/CodeGen/RISCV/rv32zbp.ll
  llvm/test/CodeGen/RISCV/rv32zbs.ll
  llvm/test/CodeGen/RISCV/rv32zbt.ll
  llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
  llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
  llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll
  llvm/test/CodeGen/RISCV/rv64zba.ll
  llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
  llvm/test/CodeGen/RISCV/rv64zbb.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll
  llvm/test/CodeGen/RISCV/rv64zbs.ll
  llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
  llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
  llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
  llvm/test/CodeGen/RISCV/rvv/combine-splats.ll
  llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
  llvm/test/CodeGen/RISCV/rvv/memory-args.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
  llvm/test/CodeGen/RISCV/rvv/stepvector.ll
  llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
  llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
  llvm/test/CodeGen/RISCV/sadd_sat.ll
  llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
  llvm/test/CodeGen/RISCV/select-cc.ll
  llvm/test/CodeGen/RISCV/select-const.ll
  llvm/test/CodeGen/RISCV/select-constant-xor.ll
  llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
  llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
  llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
  llvm/test/CodeGen/RISCV/shifts.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll
  llvm/test/CodeGen/RISCV/split-offsets.ll
  llvm/test/CodeGen/RISCV/split-sp-adjust.ll
  llvm/test/CodeGen/RISCV/srem-lkk.ll
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
  llvm/test/CodeGen/RISCV/ssub_sat.ll
  llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
  llvm/test/CodeGen/RISCV/stack-slot-size.ll
  llvm/test/CodeGen/RISCV/uadd_sat.ll
  llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
  llvm/test/CodeGen/RISCV/urem-lkk.ll
  llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
  llvm/test/CodeGen/RISCV/usub_sat.ll
  llvm/test/CodeGen/RISCV/usub_sat_plus.ll
  llvm/test/CodeGen/RISCV/vararg.ll
  llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
  llvm/test/CodeGen/RISCV/xaluo.ll
  llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
  llvm/test/MC/RISCV/compress-rv32i.s
  llvm/test/MC/RISCV/numeric-reg-names.s
  llvm/test/MC/RISCV/rv32i-aliases-valid.s
  llvm/test/MC/RISCV/rv64i-aliases-valid.s
  llvm/test/MC/RISCV/rv64zba-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbs-aliases-valid.s
  llvm/test/MC/RISCV/rvi-aliases-valid.s
  llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/riscv_function_name.ll.expected

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