[PATCH] D106449: [amdgpu] Handle the case where there is no scavenged register.

[Michael Liao via Phabricator via llvm-commits]

hliao added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=5 -o - %s | FileCheck %s
 
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arsenm wrote:
> Can you switch this to an amdhsa triple? I want to be sure the use of the sgpr0_sgpr1 ordinarily used for the scratch buffer is tested. I think you would need to add a test variant that is a non-kernel function too
that none-kernel case is added. however, due to calling convention, v0 is reused for spilling SGPR and is always available for spilling SGPRs. We cannot test the no-scavenged register case. Do you have suggestions to fabricate the test case for that purpose?


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https://reviews.llvm.org/D106449