[PATCH] D106449: [amdgpu] Handle the case where there is no scavenged register.

[Michael Liao via Phabricator via llvm-commits]

hliao updated this revision to Diff 382756.
hliao marked 3 inline comments as done.
hliao added a comment.

Add a non-kernel function case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106449/new/

https://reviews.llvm.org/D106449

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/BranchRelaxation.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/lib/Target/AVR/AVRInstrInfo.cpp
  llvm/lib/Target/AVR/AVRInstrInfo.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D106449.382756.patch
Type: text/x-patch
Size: 89471 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20211027/087e6b63/attachment.bin>