[llvm] bffc657 - [x86] add test for vector increment; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2021-10-26T08:20:18-04:00
New Revision: bffc6574971e22a470c2114c865b29ccb9cfe3d7

URL: https://github.com/llvm/llvm-project/commit/bffc6574971e22a470c2114c865b29ccb9cfe3d7
DIFF: https://github.com/llvm/llvm-project/commit/bffc6574971e22a470c2114c865b29ccb9cfe3d7.diff

LOG: [x86] add test for vector increment; NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/combine-sub.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/X86/combine-sub.ll b/llvm/test/CodeGen/X86/combine-sub.ll
index 48a819d7e3c4..a399c5175dd6 100644
--- a/llvm/test/CodeGen/X86/combine-sub.ll
+++ b/llvm/test/CodeGen/X86/combine-sub.ll
@@ -276,6 +276,32 @@ define <4 x i32> @combine_vec_neg_xor_consts(<4 x i32> %x) {
   ret <4 x i32> %sub
 }
 
+define void @PR52032_oneuse_constant(<8 x i32>* %p) {
+; SSE-LABEL: PR52032_oneuse_constant:
+; SSE:       # %bb.0:
+; SSE-NEXT:    movdqu (%rdi), %xmm0
+; SSE-NEXT:    movdqu 16(%rdi), %xmm1
+; SSE-NEXT:    pcmpeqd %xmm2, %xmm2
+; SSE-NEXT:    psubd %xmm2, %xmm1
+; SSE-NEXT:    psubd %xmm2, %xmm0
+; SSE-NEXT:    movdqu %xmm0, (%rdi)
+; SSE-NEXT:    movdqu %xmm1, 16(%rdi)
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: PR52032_oneuse_constant:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vmovdqu (%rdi), %ymm0
+; AVX-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX-NEXT:    vpsubd %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vmovdqu %ymm0, (%rdi)
+; AVX-NEXT:    vzeroupper
+; AVX-NEXT:    retq
+  %i3 = load <8 x i32>, <8 x i32>* %p, align 4
+  %i4 = add nsw <8 x i32> %i3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+  store <8 x i32> %i4, <8 x i32>* %p, align 4
+  ret void
+}
+
 define void @PR52032(<8 x i32>* %p) {
 ; SSE-LABEL: PR52032:
 ; SSE:       # %bb.0: