[PATCH] D111638: [AArch64][SVE] Combine predicated FMUL/FADD into FMA

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:719
+  llvm::FastMathFlags FAddFlags = II.getFastMathFlags();
+  llvm::FastMathFlags FMulFlags = cast<IntrinsicInst>(FMul)->getFastMathFlags();
+  bool AllowReassoc = FAddFlags.allowReassoc() && FMulFlags.allowReassoc();
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It looks like you've dropped FAddFlags != FMulFlags, and it looks like we need a test for that case.


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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:763
+static Optional<Instruction *> instCombineSVEVectorFAdd(InstCombiner &IC,
+                                                        IntrinsicInst &IIs) {
+  auto FMLA = instCombineSVEVectorFMLA(IC, II);
----------------
stray 's'


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111638/new/

https://reviews.llvm.org/D111638