[PATCH] D112466: [NVPTX] Annotate LDG/LDU instructions as mayLoad

[Justin Lebar via Phabricator via llvm-commits]

jlebar added a comment.

> It appears that mayLoad was omitted for a reason, but I cannot figure out why. If a load is done from a read-only memory, it should still be treated as a load, right?

I think the notion is, if the load is from read-only memory that always has the same value for the entirety of the program, in what way is it like a "load", as opposed to e.g. "move immediate into register"?

You can safely reorder these instructions with any other memory operation.

Definitely a hack, and maybe there is today a better way of representing this in LLVM.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112466/new/

https://reviews.llvm.org/D112466