[PATCH] D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0

Mon Oct 25 02:16:14 PDT 2021

RKSimon added a comment.

In D111530#3083495 <https://reviews.llvm.org/D111530#3083495>, @fzhinkin wrote:

> Handling of trees generated during legalization of i128/i256/etc to i32 is relatively simple, but in case of i686 some of these expressions are folded into funnel shifts before `SimplifySetCC` is applied to setcc.
> I see two options here (but I'm far from being an expert, so correct me if I'm wrong and there are simpler alternatives):
>
> 1. support various instructions (funnel shifts, rotations, bit/byte swaps) in `TargetLowering::optimizeSetCCOfExpandedShift` in addition to SHL/SRL;
> 2. support only SHL/SRL in `TargetLowering::optimizeSetCCOfExpandedShift` and apply it in `DAGTypeLegalizer::IntegerExpandSetCCOperands` right after setcc's operands expansion.
>
> Personally I'm leaning towards second option as it should be less fragile and easier to maintain.

Makes sense to try (2) first - although I expect at least partial support for (1) might end up being required - you are handling a pattern that is almost a funnel shift much of the time.

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https://reviews.llvm.org/D111530