[PATCH] D112323: GlobalISel/Utils: Use incoming regbank while constraining the superclasses

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas created this revision.
cdevadas added reviewers: aemerson, dsanders, aditya_nandakumar, arsenm, foad.
Herald added subscribers: kerbowa, hiraditya, tpr, rovka, nhaehnle, jvesely.
cdevadas requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

Register operands with superclasses can possibly have multiple regBanks
if they have different register types. The regBank ambiguity resolved
during regbankselect should be used to constrain the operand regclass
instead of obtaining one from the MCInstrDesc.

This is a prerequisite patch for D109300 <https://reviews.llvm.org/D109300> that introduces allocatable AV_*
Superclasses for AMDGPU by combining both VGPRs and AGPRs and we want to
restrain the regclass to either A or V based on the incoming regbank.
It would otherwise lead to incorrect codegen.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112323

Files:
  llvm/lib/CodeGen/GlobalISel/Utils.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir

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