[PATCH] D110841: [AArch64] Remove redundant ORRWrs which is generated by zero-extend
JinGu Kang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 20 06:32:17 PDT 2021
jaykang10 added a comment.
In D110841#3074973 <https://reviews.llvm.org/D110841#3074973>, @dmgreen wrote:
> Do we need to remove Kill flags from the uses of the register we are replacing? From something like this:
>
> target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
> target triple = "aarch64-none-none-eabi"
>
> @e = dso_local local_unnamed_addr global i16 0, align 4
> @b = dso_local local_unnamed_addr global i32 0, align 4
> @d = dso_local local_unnamed_addr global i32 0, align 4
> @c = dso_local local_unnamed_addr global i32* null, align 8
> @a = dso_local local_unnamed_addr global i32 0, align 4
>
> define i32 @i() {
> entry:
> %0 = load i32, i32* @b, align 4
> %1 = trunc i32 %0 to i16
> %conv1 = and i16 %1, 255
> %2 = load i32, i32* @d, align 4
> %tobool.not = icmp eq i32 %2, 0
> br i1 %tobool.not, label %if.end, label %if.then
>
> if.then: ; preds = %entry
> %conv2 = zext i16 %conv1 to i64
> %3 = inttoptr i64 %conv2 to i32*
> store i32* %3, i32** @c, align 8
> br label %if.end
>
> if.end: ; preds = %if.then, %entry
> %4 = load i32, i32* @a, align 4
> %5 = trunc i32 %4 to i16
> %conv4 = or i16 %conv1, %5
> store i16 %conv4, i16* @e, align 4
> ret i32 0
> }
You are right! We need to clear the kill flag of the source register of the ORRWrs. I was confused with the bitmask peephole opt case.
Let me clear the kill flag. Thanks for catching that. @dmgreen
================
Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:240
+
+ Register DefReg = MI.getOperand(0).getReg();
+ MRI->replaceRegWith(DefReg, MI.getOperand(2).getReg());
----------------
dmgreen wrote:
> Can we add a dbgs() output explaining what was removed?
Yep, let me add debug output.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D110841/new/
https://reviews.llvm.org/D110841
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