[PATCH] D110841: [AArch64] Remove redundant ORRWrs which is generated by zero-extend

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Do we need to remove Kill flags from the uses of the register we are replacing? From something like this:

  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64-none-none-eabi"
  
  @e = dso_local local_unnamed_addr global i16 0, align 4
  @b = dso_local local_unnamed_addr global i32 0, align 4
  @d = dso_local local_unnamed_addr global i32 0, align 4
  @c = dso_local local_unnamed_addr global i32* null, align 8
  @a = dso_local local_unnamed_addr global i32 0, align 4
  
  define i32 @i() {
  entry:
    %0 = load i32, i32* @b, align 4
    %1 = trunc i32 %0 to i16
    %conv1 = and i16 %1, 255
    %2 = load i32, i32* @d, align 4
    %tobool.not = icmp eq i32 %2, 0
    br i1 %tobool.not, label %if.end, label %if.then
  
    if.then:                                          ; preds = %entry
    %conv2 = zext i16 %conv1 to i64
    %3 = inttoptr i64 %conv2 to i32*
    store i32* %3, i32** @c, align 8
    br label %if.end
  
    if.end:                                           ; preds = %if.then, %entry
    %4 = load i32, i32* @a, align 4
    %5 = trunc i32 %4 to i16
    %conv4 = or i16 %conv1, %5
    store i16 %conv4, i16* @e, align 4
    ret i32 0
  }



================
Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:240
+
+  Register DefReg = MI.getOperand(0).getReg();
+  MRI->replaceRegWith(DefReg, MI.getOperand(2).getReg());
----------------
Can we add a dbgs() output explaining what was removed?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110841/new/

https://reviews.llvm.org/D110841