[PATCH] D110841: [AArch64] Remove redundant ORRWrs which is generated by zero-extend

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 added a comment.

In D110841#3074725 <https://reviews.llvm.org/D110841#3074725>, @dmgreen wrote:

> Thanks.
>
> I assume you have checked through the AArch64 pseudo instructions (the ones before `ABS_ZPmZ_B` in `build/lib/Target/AArch64/AArch64GenInstrInfo.inc`) and they look OK? They will follow the same rules of producing zeroed upper bits for W register definitions.

um... I have checked the pseudo MIs which inherits `Pseudo` class in the AArch64InstrInfo.td and AArch64InstrFormats.td files and `expandMI` function in `AArch64ExpandPseudoInsts.cpp`. I was able to see the pseudo MIs are expanded to the AArch64 MIs... and I thought they follows the rule.

If you feel some pseudo MIs do not follow the rule, please let me know. I could miss some MIs...



================
Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:21
+//
+//    There are 2 patterns for zero-extend as below.
+//
----------------
dmgreen wrote:
> I don't think that representing this in terms of ISel patterns is useful. It should preferably be described in terms of the Machine Instructions that will be present, no matter where they come from.
Yep, let me update the comment.


================
Comment at: llvm/test/CodeGen/AArch64/arm64-assert-zext-sext.ll:40
   br label %if.end
-; CHECK:       // %if.then
-; CHECK:       mov     w{{[0-9]+}}, w{{[0-9]+}}
----------------
dmgreen wrote:
> This looks like the kind of test we could use update_llc_test_checks on.
It looked it is pre-commit test with NFC tag.

Let me update the expected output with update_llc_test_checks.


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https://reviews.llvm.org/D110841