[PATCH] D110841: [AArch64] Remove redundant ORRWrs which is generated by zero-extend

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks.

I assume you have checked through the AArch64 pseudo instructions (the ones before `ABS_ZPmZ_B` in `build/lib/Target/AArch64/AArch64GenInstrInfo.inc`) and they look OK? They will follow the same rules of producing zeroed upper bits for W register definitions.



================
Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:21
+//
+//    There are 2 patterns for zero-extend as below.
+//
----------------
I don't think that representing this in terms of ISel patterns is useful. It should preferably be described in terms of the Machine Instructions that will be present, no matter where they come from.


================
Comment at: llvm/test/CodeGen/AArch64/arm64-assert-zext-sext.ll:40
   br label %if.end
-; CHECK:       // %if.then
-; CHECK:       mov     w{{[0-9]+}}, w{{[0-9]+}}
----------------
This looks like the kind of test we could use update_llc_test_checks on.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110841/new/

https://reviews.llvm.org/D110841