[PATCH] D109963: [AArch64] Split bitmask immediate of bitwise AND operation

Fri Oct 15 14:39:34 PDT 2021

jaykang10 added inline comments.

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Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:129
+  // Check whether AND's operand is MOV with immediate.
+  MachineInstr *MovMI = MRI->getUniqueVRegDef(MI.getOperand(2).getReg());
+  MachineInstr *SubregToRegMI = nullptr;
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craig.topper wrote:
> danielkiss wrote:
> > With the chromium codebase we found getUniqueVRegDef returns null as it could normally.
> > I'd add a check for that.
> Since this is running on SSA form, that should be getVRegDef. Is returning null because it is a physical register or for some other reason?
Sorry for bug again... 

The MI is deleted after visiting all instructions so there are multiple definitions with same register after transformation and it breaks SSA form... I found the problem when I implemented https://reviews.llvm.org/D110841... I missed to update this patch with it... I am sorry for that.

I need to check the bootstrap build. Once it is ok, I will let you know.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109963/new/

https://reviews.llvm.org/D109963