[PATCH] D109963: [AArch64] Split bitmask immediate of bitwise AND operation

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:129
+  // Check whether AND's operand is MOV with immediate.
+  MachineInstr *MovMI = MRI->getUniqueVRegDef(MI.getOperand(2).getReg());
+  MachineInstr *SubregToRegMI = nullptr;
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danielkiss wrote:
> With the chromium codebase we found getUniqueVRegDef returns null as it could normally.
> I'd add a check for that.
Since this is running on SSA form, that should be getVRegDef. Is returning null because it is a physical register or for some other reason?


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  https://reviews.llvm.org/D109963/new/

https://reviews.llvm.org/D109963