[PATCH] D111904: [RISCV] Lower fixed vector CTLZ_ZERO_UNDEF by converting to FP and extracting the exponent.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 15 11:40:06 PDT 2021
craig.topper added inline comments.
================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:7065
SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
- Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
- DAG.getConstant(NumBitsPerElt, dl, VT), CTLZ);
+ Result = DAG.getSelect(dl, VT, SrcIsZero,
+ DAG.getConstant(NumBitsPerElt, dl, VT), CTLZ);
----------------
This is needed to get VSELECT for vectors.
================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:7117
SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
- Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
- DAG.getConstant(NumBitsPerElt, dl, VT), CTTZ);
+ Result = DAG.getSelect(dl, VT, SrcIsZero,
+ DAG.getConstant(NumBitsPerElt, dl, VT), CTTZ);
----------------
This isn't tested by this patch but makes it consistent with CTLZ.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D111904/new/
https://reviews.llvm.org/D111904
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