[PATCH] D109144: [SPIR-V] Add SPIR-V triple architecture and clang target info
Anastasia Stulova via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 14 05:48:18 PDT 2021
Anastasia added a comment.
In D109144#3063255 <https://reviews.llvm.org/D109144#3063255>, @linjamaki wrote:
>> Can you explain what does this mean
>
> It was trying to clarify a potential misunderstanding of how programs are compiled when HIPSPV is targeted: For HIPSPV, the SPIR-V code generation is done by the clang driver. When we compile HIP programs for HIPCL or the HIPLZ runtime, we issue a single clang command such as this:
>
> clang++ --offload=spirv64 foo.hip -l<hip-runtime> -o foo
>
> With this, the clang driver compiles the device side code to a SPIR-V binary and then compiles host side code, and embeds the SPIR-V binary to the host (fat) binary.
>
>> ? In the tests I can see the following `--offload=spirv64` which does feel like it is specified explicitly that the target is SPIR-V...
>
> For HIPSPV the `--offload` option is used to specify the device code target but the end result is a host binary (e.g. x86_64) with device code (SPIR-V binary) embedded in it. We need a way to specify the device code target to be other than the currently fixed `amdgcn-amd-amdhsa` and using the `--offload` switch is a solution we are suggesting here.
Thanks for the clarifications. So it seems that you are not expecting that the device target triple is being explicitly passed anywhere then and that means you pass the device triple implicitly? Although your `--offload` option does seem conceptually like a device target triple, so I wonder if better naming for it would be `--offload-target`? Would it work for you if we introduce SPIR-V triple explicitly and you use it as a device offload triple? It would probably makes sense to use the same triple to targeting SPIR-V generation by everyone? However I appreciate that OpenCL flow would be somewhat different since it doesn't have a split into host and device but only contains device compilation phase...
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https://reviews.llvm.org/D109144/new/
https://reviews.llvm.org/D109144
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