[PATCH] D111502: [TableGen] Fix both sides of '&&' are same

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, kparzysz, xbolva00.
Herald added subscribers: luismarques, s.egerton, PkmX, simoncook.
craig.topper requested review of this revision.
Herald added a project: LLVM.

The operand of the second any_of in EnforceSmallerThan should be
B not S like the FP code in the if below.

Unfortunately, fixing that causes an infinite loop in the build
of RISCV. So I've added a workaround for that as well.

Fixes PR44768.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111502

Files:
  llvm/utils/TableGen/CodeGenDAGPatterns.cpp
  llvm/utils/TableGen/CodeGenDAGPatterns.h


Index: llvm/utils/TableGen/CodeGenDAGPatterns.h
===================================================================
--- llvm/utils/TableGen/CodeGenDAGPatterns.h
+++ llvm/utils/TableGen/CodeGenDAGPatterns.h
@@ -299,7 +299,8 @@
   bool EnforceAny(TypeSetByHwMode &Out);
   /// Make sure that for each type in \p Small, there exists a larger type
   /// in \p Big.
-  bool EnforceSmallerThan(TypeSetByHwMode &Small, TypeSetByHwMode &Big);
+  bool EnforceSmallerThan(TypeSetByHwMode &Small, TypeSetByHwMode &Big,
+                          bool SmallIsVT = false);
   /// 1. Ensure that for each type T in \p Vec, T is a vector type, and that
   ///    for each type U in \p Elem, U is a scalar type.
   /// 2. Ensure that for each (scalar) type U in \p Elem, there exists a
Index: llvm/utils/TableGen/CodeGenDAGPatterns.cpp
===================================================================
--- llvm/utils/TableGen/CodeGenDAGPatterns.cpp
+++ llvm/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -451,8 +451,8 @@
 }
 
 /// Make sure that for each type in Small, there exists a larger type in Big.
-bool TypeInfer::EnforceSmallerThan(TypeSetByHwMode &Small,
-                                   TypeSetByHwMode &Big) {
+bool TypeInfer::EnforceSmallerThan(TypeSetByHwMode &Small, TypeSetByHwMode &Big,
+                                   bool SmallIsVT) {
   ValidateOnExit _1(Small, *this), _2(Big, *this);
   if (TP.hasError())
     return false;
@@ -476,7 +476,7 @@
     TypeSetByHwMode::SetType &S = Small.get(M);
     TypeSetByHwMode::SetType &B = Big.get(M);
 
-    if (any_of(S, isIntegerOrPtr) && any_of(S, isIntegerOrPtr)) {
+    if (any_of(S, isIntegerOrPtr) && any_of(B, isIntegerOrPtr)) {
       auto NotInt = [](MVT VT) { return !isIntegerOrPtr(VT); };
       Changed |= berase_if(S, NotInt);
       Changed |= berase_if(B, NotInt);
@@ -485,7 +485,9 @@
       Changed |= berase_if(S, NotFP);
       Changed |= berase_if(B, NotFP);
     } else if (S.empty() || B.empty()) {
-      Changed = !S.empty() || !B.empty();
+      // If small is a VT, S will always be populated before this method is
+      // called so it will never be empty. Don't report that as a change.
+      Changed = (!SmallIsVT && !S.empty()) || !B.empty();
       S.clear();
       B.clear();
     } else {
@@ -1637,7 +1639,8 @@
       getOperandNum(x.SDTCisVTSmallerThanOp_Info.OtherOperandNum, N, NodeInfo,
                     OResNo);
 
-    return TI.EnforceSmallerThan(TypeListTmp, OtherNode->getExtType(OResNo));
+    return TI.EnforceSmallerThan(TypeListTmp, OtherNode->getExtType(OResNo),
+                                 /*SmallIsVT*/ true);
   }
   case SDTCisOpSmallerThanOp: {
     unsigned BResNo = 0;


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