[llvm] 27c57e7 - [TwoAddressInstruction] Enable machine verification after this pass
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 7 12:07:43 PDT 2021
Author: Jay Foad
Date: 2021-10-07T20:04:51+01:00
New Revision: 27c57e791a0af914792404a157f8022e91187a33
URL: https://github.com/llvm/llvm-project/commit/27c57e791a0af914792404a157f8022e91187a33
DIFF: https://github.com/llvm/llvm-project/commit/27c57e791a0af914792404a157f8022e91187a33.diff
LOG: [TwoAddressInstruction] Enable machine verification after this pass
Differential Revision: https://reviews.llvm.org/D111007
Added:
Modified:
llvm/lib/CodeGen/TargetPassConfig.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 3edbc2b4bfd6..b169ce628ce0 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -1418,7 +1418,7 @@ bool TargetPassConfig::usingDefaultRegAlloc() const {
/// register allocation. No coalescing or scheduling.
void TargetPassConfig::addFastRegAlloc() {
addPass(&PHIEliminationID);
- addPass(&TwoAddressInstructionPassID, false);
+ addPass(&TwoAddressInstructionPassID);
addRegAssignAndRewriteFast();
}
@@ -1452,7 +1452,7 @@ void TargetPassConfig::addOptimizedRegAlloc() {
if (EarlyLiveIntervals)
addPass(&LiveIntervalsID);
- addPass(&TwoAddressInstructionPassID, false);
+ addPass(&TwoAddressInstructionPassID);
addPass(&RegisterCoalescerID);
// The machine scheduler may accidentally create disconnected components
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