[llvm] 42ba79b - [AArch64][SME] Update tile slice index offset
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 7 01:55:42 PDT 2021
Author: Cullen Rhodes
Date: 2021-10-07T08:55:10Z
New Revision: 42ba79b7b025c97c3aff2b958f18be90e70239f2
URL: https://github.com/llvm/llvm-project/commit/42ba79b7b025c97c3aff2b958f18be90e70239f2
DIFF: https://github.com/llvm/llvm-project/commit/42ba79b7b025c97c3aff2b958f18be90e70239f2.diff
LOG: [AArch64][SME] Update tile slice index offset
Changes in architecture revision 00eac1:
* Tile slice index offset no longer prefixed with '#'.
* The syntax for 128-bit (.Q) ZA tile slice accesses must now include
an explicit zero index.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-09
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D111212
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
llvm/lib/Target/AArch64/SMEInstrFormats.td
llvm/test/MC/AArch64/SME/ld1b-diagnostics.s
llvm/test/MC/AArch64/SME/ld1b.s
llvm/test/MC/AArch64/SME/ld1d-diagnostics.s
llvm/test/MC/AArch64/SME/ld1d.s
llvm/test/MC/AArch64/SME/ld1h-diagnostics.s
llvm/test/MC/AArch64/SME/ld1h.s
llvm/test/MC/AArch64/SME/ld1q-diagnostics.s
llvm/test/MC/AArch64/SME/ld1q.s
llvm/test/MC/AArch64/SME/ld1w-diagnostics.s
llvm/test/MC/AArch64/SME/ld1w.s
llvm/test/MC/AArch64/SME/ldr.s
llvm/test/MC/AArch64/SME/mova-diagnostics.s
llvm/test/MC/AArch64/SME/mova.s
llvm/test/MC/AArch64/SME/st1b-diagnostics.s
llvm/test/MC/AArch64/SME/st1b.s
llvm/test/MC/AArch64/SME/st1d-diagnostics.s
llvm/test/MC/AArch64/SME/st1d.s
llvm/test/MC/AArch64/SME/st1h-diagnostics.s
llvm/test/MC/AArch64/SME/st1h.s
llvm/test/MC/AArch64/SME/st1q-diagnostics.s
llvm/test/MC/AArch64/SME/st1q.s
llvm/test/MC/AArch64/SME/st1w-diagnostics.s
llvm/test/MC/AArch64/SME/st1w.s
llvm/test/MC/AArch64/SME/str.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 939880de03145..33ce7df2bddad 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -721,6 +721,7 @@ def tvecshiftR64 : Operand<i32>, TImmLeaf<i32, [{
let ParserMatchClass = Imm1_64Operand;
}
+def Imm0_0Operand : AsmImmRange<0, 0>;
def Imm0_1Operand : AsmImmRange<0, 1>;
def Imm0_3Operand : AsmImmRange<0, 3>;
def Imm0_7Operand : AsmImmRange<0, 7>;
@@ -1294,6 +1295,37 @@ defm sve_elm_idx_extdup_q
: VectorIndex<i64, SVEVectorIndexExtDupQOperand,
[{ return ((uint64_t)Imm) < 4; }]>;
+def sme_elm_idx0_0 : Operand<i64>, ImmLeaf<i64, [{
+ return ((uint64_t)Imm) == 0;
+}]> {
+ let ParserMatchClass = Imm0_0Operand;
+ let PrintMethod = "printMatrixIndex";
+}
+def sme_elm_idx0_1 : Operand<i64>, ImmLeaf<i64, [{
+ return ((uint64_t)Imm) <= 1;
+}]> {
+ let ParserMatchClass = Imm0_1Operand;
+ let PrintMethod = "printMatrixIndex";
+}
+def sme_elm_idx0_3 : Operand<i64>, ImmLeaf<i64, [{
+ return ((uint64_t)Imm) <= 3;
+}]> {
+ let ParserMatchClass = Imm0_3Operand;
+ let PrintMethod = "printMatrixIndex";
+}
+def sme_elm_idx0_7 : Operand<i64>, ImmLeaf<i64, [{
+ return ((uint64_t)Imm) <= 7;
+}]> {
+ let ParserMatchClass = Imm0_7Operand;
+ let PrintMethod = "printMatrixIndex";
+}
+def sme_elm_idx0_15 : Operand<i64>, ImmLeaf<i64, [{
+ return ((uint64_t)Imm) <= 15;
+}]> {
+ let ParserMatchClass = Imm0_15Operand;
+ let PrintMethod = "printMatrixIndex";
+}
+
// 8-bit immediate for AdvSIMD where 64-bit values of the form:
// aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
// are encoded as the eight bit value 'abcdefgh'.
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 1d4033b1f3766..aa3fe27c011b9 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -5058,6 +5058,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
return Error(Loc, "index must be a multiple of 8 in range [0, 32760].");
case Match_InvalidMemoryIndexed16:
return Error(Loc, "index must be a multiple of 16 in range [0, 65520].");
+ case Match_InvalidImm0_0:
+ return Error(Loc, "immediate must be 0.");
case Match_InvalidImm0_1:
return Error(Loc, "immediate must be an integer in range [0, 1].");
case Match_InvalidImm0_3:
@@ -5692,6 +5694,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidMemoryIndexedSImm9:
case Match_InvalidMemoryIndexed16SImm9:
case Match_InvalidMemoryIndexed8SImm10:
+ case Match_InvalidImm0_0:
case Match_InvalidImm0_1:
case Match_InvalidImm0_3:
case Match_InvalidImm0_7:
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 96cbbed871fec..0bb6ab57c8bc4 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -323,6 +323,22 @@ DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
// ^ insert implicit 8-bit element tile
MI.insert(MI.begin()+2, MCOperand::createReg(AArch64::ZAB0));
break;
+ case AArch64::LD1_MXIPXX_H_Q:
+ case AArch64::LD1_MXIPXX_V_Q:
+ case AArch64::ST1_MXIPXX_H_Q:
+ case AArch64::ST1_MXIPXX_V_Q:
+ // 128-bit load/store have implicit zero vector index.
+ MI.insert(MI.begin()+2, MCOperand::createImm(0));
+ break;
+ // 128-bit mova have implicit zero vector index.
+ case AArch64::INSERT_MXIPZ_H_Q:
+ case AArch64::INSERT_MXIPZ_V_Q:
+ MI.insert(MI.begin()+2, MCOperand::createImm(0));
+ break;
+ case AArch64::EXTRACT_ZPMXI_H_Q:
+ case AArch64::EXTRACT_ZPMXI_V_Q:
+ MI.addOperand(MCOperand::createImm(0));
+ break;
case AArch64::SMOVvi8to32_idx0:
case AArch64::SMOVvi8to64_idx0:
case AArch64::SMOVvi16to32_idx0:
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index bebff71ddbf20..f7920d7932593 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -1450,6 +1450,12 @@ void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
O << "[" << MI->getOperand(OpNum).getImm() << "]";
}
+void AArch64InstPrinter::printMatrixIndex(const MCInst *MI, unsigned OpNum,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ O << MI->getOperand(OpNum).getImm();
+}
+
void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, uint64_t Address,
unsigned OpNum,
const MCSubtargetInfo &STI,
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
index 9ec74a1bc7b65..d36fb30a0ce66 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
@@ -161,6 +161,8 @@ class AArch64InstPrinter : public MCInstPrinter {
void printVectorIndex(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
+ void printMatrixIndex(const MCInst *MI, unsigned OpNum,
+ const MCSubtargetInfo &STI, raw_ostream &O);
void printAdrpLabel(const MCInst *MI, uint64_t Address, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printBarrierOption(const MCInst *MI, unsigned OpNum,
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index 00fd374587bc2..6b339cbbb66e7 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -180,26 +180,18 @@ class sme_mem_ld_ss_base<bit Q, bit V, bits<2> msz, dag outs, dag ins,
let mayLoad = 1;
}
-class sme_mem_ld_ss_inst_BHSD<bits<2> msz, string mnemonic,
- MatrixTileVectorOperand tile_ty, bit is_col,
- Operand imm_ty, RegisterOperand gpr_ty>
+class sme_mem_ld_ss_inst<bit Q, bits<2> msz, string mnemonic,
+ MatrixTileVectorOperand tile_ty, bit is_col,
+ Operand imm_ty, RegisterOperand gpr_ty>
: sme_mem_ld_ss_base<
- 0b0, is_col, msz, (outs tile_ty:$ZAt),
+ Q, is_col, msz, (outs tile_ty:$ZAt),
(ins MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn,
gpr_ty:$Rm),
mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg/z, [$Rn, $Rm]">;
-class sme_mem_ld_ss_inst_Q<string mnemonic, MatrixTileVectorOperand tile_ty,
- bit is_col>
- : sme_mem_ld_ss_base<
- 0b1, is_col, 0b11, (outs tile_ty:$ZAt),
- (ins MatrixIndexGPR32Op12_15:$Rv, PPR3bAny:$Pg, GPR64sp:$Rn,
- GPR64shifted128:$Rm),
- mnemonic, "\t\\{$ZAt[$Rv]\\}, $Pg/z, [$Rn, $Rm]">;
-
-multiclass sme_mem_ss_aliases_BHSD<string mnemonic, Instruction inst,
- MatrixTileVectorOperand tile_ty, Operand imm_ty,
- RegisterOperand gpr_ty,
+multiclass sme_mem_ss_aliases_base<string mnemonic, Instruction inst,
+ MatrixTileVectorOperand tile_ty,
+ Operand imm_ty, RegisterOperand gpr_ty,
string pg_suffix=""> {
def : InstAlias<mnemonic # "\t$ZAt[$Rv, $imm], $Pg" # pg_suffix # ", [$Rn, $Rm]",
(inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, gpr_ty:$Rm), 0>;
@@ -210,35 +202,23 @@ multiclass sme_mem_ss_aliases_BHSD<string mnemonic, Instruction inst,
(inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>;
}
-multiclass sme_mem_ss_aliases_Q<string mnemonic, Instruction inst,
- MatrixTileVectorOperand tile_ty,
- string pg_suffix=""> {
- def : InstAlias<mnemonic # "\t$ZAt[$Rv], $Pg" # pg_suffix # ", [$Rn, $Rm]",
- (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, PPR3bAny:$Pg, GPR64sp:$Rn, GPR64shifted128:$Rm), 0>;
- // Default XZR offset aliases
- def : InstAlias<mnemonic # "\t\\{$ZAt[$Rv]\\}, $Pg" # pg_suffix # ", [$Rn]",
- (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 2>;
- def : InstAlias<mnemonic # "\t$ZAt[$Rv], $Pg" # pg_suffix # ", [$Rn]",
- (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>;
-}
-
multiclass sme_mem_ss_aliases<string mnemonic, string inst, bit is_col,
string pg_suffix=""> {
- defm : sme_mem_ss_aliases_BHSD<mnemonic # "b", !cast<Instruction>(inst # _B),
+ defm : sme_mem_ss_aliases_base<mnemonic # "b", !cast<Instruction>(inst # _B),
!if(is_col, TileVectorOpV8, TileVectorOpH8),
- imm0_15, GPR64shifted8, pg_suffix>;
- defm : sme_mem_ss_aliases_BHSD<mnemonic # "h", !cast<Instruction>(inst # _H),
+ sme_elm_idx0_15, GPR64shifted8, pg_suffix>;
+ defm : sme_mem_ss_aliases_base<mnemonic # "h", !cast<Instruction>(inst # _H),
!if(is_col, TileVectorOpV16, TileVectorOpH16),
- imm0_7, GPR64shifted16, pg_suffix>;
- defm : sme_mem_ss_aliases_BHSD<mnemonic # "w", !cast<Instruction>(inst # _S),
+ sme_elm_idx0_7, GPR64shifted16, pg_suffix>;
+ defm : sme_mem_ss_aliases_base<mnemonic # "w", !cast<Instruction>(inst # _S),
!if(is_col, TileVectorOpV32, TileVectorOpH32),
- imm0_3, GPR64shifted32, pg_suffix>;
- defm : sme_mem_ss_aliases_BHSD<mnemonic # "d", !cast<Instruction>(inst # _D),
+ sme_elm_idx0_3, GPR64shifted32, pg_suffix>;
+ defm : sme_mem_ss_aliases_base<mnemonic # "d", !cast<Instruction>(inst # _D),
!if(is_col, TileVectorOpV64, TileVectorOpH64),
- imm0_1, GPR64shifted64, pg_suffix>;
- defm : sme_mem_ss_aliases_Q <mnemonic # "q", !cast<Instruction>(inst # _Q),
+ sme_elm_idx0_1, GPR64shifted64, pg_suffix>;
+ defm : sme_mem_ss_aliases_base<mnemonic # "q", !cast<Instruction>(inst # _Q),
!if(is_col, TileVectorOpV128, TileVectorOpH128),
- pg_suffix>;
+ sme_elm_idx0_0, GPR64shifted128, pg_suffix>;
}
multiclass sme_mem_ld_ss_aliases<string inst, bit is_col> {
@@ -246,44 +226,39 @@ multiclass sme_mem_ld_ss_aliases<string inst, bit is_col> {
}
multiclass sme_mem_ld_v_ss<string mnemonic, bit is_col> {
- def _B : sme_mem_ld_ss_inst_BHSD<0b00, mnemonic # "b",
- !if(is_col, TileVectorOpV8,
- TileVectorOpH8),
- is_col, imm0_15, GPR64shifted8> {
+ def _B : sme_mem_ld_ss_inst<0b0, 0b00, mnemonic # "b",
+ !if(is_col, TileVectorOpV8, TileVectorOpH8),
+ is_col, sme_elm_idx0_15, GPR64shifted8> {
bits<4> imm;
let Inst{3-0} = imm;
}
- def _H : sme_mem_ld_ss_inst_BHSD<0b01, mnemonic # "h",
- !if(is_col, TileVectorOpV16,
- TileVectorOpH16),
- is_col, imm0_7, GPR64shifted16> {
+ def _H : sme_mem_ld_ss_inst<0b0, 0b01, mnemonic # "h",
+ !if(is_col, TileVectorOpV16, TileVectorOpH16),
+ is_col, sme_elm_idx0_7, GPR64shifted16> {
bits<1> ZAt;
bits<3> imm;
let Inst{3} = ZAt;
let Inst{2-0} = imm;
}
- def _S : sme_mem_ld_ss_inst_BHSD<0b10, mnemonic # "w",
- !if(is_col, TileVectorOpV32,
- TileVectorOpH32),
- is_col, imm0_3, GPR64shifted32> {
+ def _S : sme_mem_ld_ss_inst<0b0, 0b10, mnemonic # "w",
+ !if(is_col, TileVectorOpV32, TileVectorOpH32),
+ is_col, sme_elm_idx0_3, GPR64shifted32> {
bits<2> ZAt;
bits<2> imm;
let Inst{3-2} = ZAt;
let Inst{1-0} = imm;
}
- def _D : sme_mem_ld_ss_inst_BHSD<0b11, mnemonic # "d",
- !if(is_col, TileVectorOpV64,
- TileVectorOpH64),
- is_col, imm0_1, GPR64shifted64> {
+ def _D : sme_mem_ld_ss_inst<0b0, 0b11, mnemonic # "d",
+ !if(is_col, TileVectorOpV64, TileVectorOpH64),
+ is_col, sme_elm_idx0_1, GPR64shifted64> {
bits<3> ZAt;
bits<1> imm;
let Inst{3-1} = ZAt;
let Inst{0} = imm;
}
- def _Q : sme_mem_ld_ss_inst_Q<mnemonic # "q",
- !if(is_col, TileVectorOpV128,
- TileVectorOpH128),
- is_col> {
+ def _Q : sme_mem_ld_ss_inst<0b1, 0b11, mnemonic # "q",
+ !if(is_col, TileVectorOpV128, TileVectorOpH128),
+ is_col, sme_elm_idx0_0, GPR64shifted128> {
bits<4> ZAt;
let Inst{3-0} = ZAt;
}
@@ -322,66 +297,53 @@ class sme_mem_st_ss_base<bit Q, bit V, bits<2> msz, dag ins,
let hasSideEffects = 1;
}
-class sme_mem_st_ss_inst_BHSD<bits<2> msz, string mnemonic,
- MatrixTileVectorOperand tile_ty, bit is_col,
- Operand imm_ty, RegisterOperand gpr_ty>
+class sme_mem_st_ss_inst<bit Q, bits<2> msz, string mnemonic,
+ MatrixTileVectorOperand tile_ty, bit is_col,
+ Operand imm_ty, RegisterOperand gpr_ty>
: sme_mem_st_ss_base<
- 0b0, is_col, msz,
+ Q, is_col, msz,
(ins tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg,
GPR64sp:$Rn, gpr_ty:$Rm),
mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg, [$Rn, $Rm]">;
-class sme_mem_st_ss_inst_Q<string mnemonic, MatrixTileVectorOperand tile_ty,
- bit is_col>
- : sme_mem_st_ss_base<
- 0b1, is_col, 0b11,
- (ins tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, PPR3bAny:$Pg,
- GPR64sp:$Rn, GPR64shifted128:$Rm),
- mnemonic, "\t\\{$ZAt[$Rv]\\}, $Pg, [$Rn, $Rm]">;
-
multiclass sme_mem_st_ss_aliases<string inst, bit is_col> {
defm NAME : sme_mem_ss_aliases<"st1", inst, is_col>;
}
multiclass sme_mem_st_v_ss<string mnemonic, bit is_col> {
- def _B : sme_mem_st_ss_inst_BHSD<0b00, mnemonic # "b",
- !if(is_col, TileVectorOpV8,
- TileVectorOpH8),
- is_col, imm0_15, GPR64shifted8> {
+ def _B : sme_mem_st_ss_inst<0b0, 0b00, mnemonic # "b",
+ !if(is_col, TileVectorOpV8, TileVectorOpH8),
+ is_col, sme_elm_idx0_15, GPR64shifted8> {
bits<4> imm;
let Inst{3-0} = imm;
}
- def _H : sme_mem_st_ss_inst_BHSD<0b01, mnemonic # "h",
- !if(is_col, TileVectorOpV16,
- TileVectorOpH16),
- is_col, imm0_7, GPR64shifted16> {
+ def _H : sme_mem_st_ss_inst<0b0, 0b01, mnemonic # "h",
+ !if(is_col, TileVectorOpV16, TileVectorOpH16),
+ is_col, sme_elm_idx0_7, GPR64shifted16> {
bits<1> ZAt;
bits<3> imm;
let Inst{3} = ZAt;
let Inst{2-0} = imm;
}
- def _S : sme_mem_st_ss_inst_BHSD<0b10, mnemonic # "w",
- !if(is_col, TileVectorOpV32,
- TileVectorOpH32),
- is_col, imm0_3, GPR64shifted32> {
+ def _S : sme_mem_st_ss_inst<0b0, 0b10, mnemonic # "w",
+ !if(is_col, TileVectorOpV32, TileVectorOpH32),
+ is_col, sme_elm_idx0_3, GPR64shifted32> {
bits<2> ZAt;
bits<2> imm;
let Inst{3-2} = ZAt;
let Inst{1-0} = imm;
}
- def _D : sme_mem_st_ss_inst_BHSD<0b11, mnemonic # "d",
- !if(is_col, TileVectorOpV64,
- TileVectorOpH64),
- is_col, imm0_1, GPR64shifted64> {
+ def _D : sme_mem_st_ss_inst<0b0, 0b11, mnemonic # "d",
+ !if(is_col, TileVectorOpV64, TileVectorOpH64),
+ is_col, sme_elm_idx0_1, GPR64shifted64> {
bits<3> ZAt;
bits<1> imm;
let Inst{3-1} = ZAt;
let Inst{0} = imm;
}
- def _Q : sme_mem_st_ss_inst_Q<mnemonic # "q",
- !if(is_col, TileVectorOpV128,
- TileVectorOpH128),
- is_col> {
+ def _Q : sme_mem_st_ss_inst<0b1, 0b11, mnemonic # "q",
+ !if(is_col, TileVectorOpV128, TileVectorOpH128),
+ is_col, sme_elm_idx0_0, GPR64shifted128> {
bits<4> ZAt;
let Inst{3-0} = ZAt;
}
@@ -423,13 +385,13 @@ multiclass sme_spill_fill<bit isStore, dag outs, dag ins, string opcodestr> {
def : InstAlias<opcodestr # "\t$ZAt[$Rv, $imm4], [$Rn]",
(!cast<Instruction>(NAME) MatrixOp:$ZAt,
- MatrixIndexGPR32Op12_15:$Rv, imm0_15:$imm4, GPR64sp:$Rn, 0), 1>;
+ MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0), 1>;
}
multiclass sme_spill<string opcodestr> {
defm NAME : sme_spill_fill<0b1, (outs),
(ins MatrixOp:$ZAt, MatrixIndexGPR32Op12_15:$Rv,
- imm0_15:$imm4, GPR64sp:$Rn,
+ sme_elm_idx0_15:$imm4, GPR64sp:$Rn,
imm0_15:$offset),
opcodestr>;
}
@@ -437,7 +399,7 @@ multiclass sme_spill<string opcodestr> {
multiclass sme_fill<string opcodestr> {
defm NAME : sme_spill_fill<0b0, (outs MatrixOp:$ZAt),
(ins MatrixIndexGPR32Op12_15:$Rv,
- imm0_15:$imm4, GPR64sp:$Rn,
+ sme_elm_idx0_15:$imm4, GPR64sp:$Rn,
imm0_15:$offset),
opcodestr>;
}
@@ -463,19 +425,13 @@ class sme_vector_to_tile_base<bit Q, bit V, bits<2> sz, dag outs, dag ins,
let Inst{4} = 0b0;
}
-class sme_vector_to_tile_inst<bits<2> sz, MatrixTileVectorOperand tile_ty,
+class sme_vector_to_tile_inst<bit Q, bits<2> sz, MatrixTileVectorOperand tile_ty,
bit is_col, Operand imm_ty, ZPRRegOp zpr_ty,
string mnemonic>
- : sme_vector_to_tile_base<0b0, is_col, sz, (outs tile_ty:$ZAd),
+ : sme_vector_to_tile_base<Q, is_col, sz, (outs tile_ty:$ZAd),
(ins MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, zpr_ty:$Zn),
mnemonic, "\t$ZAd[$Rv, $imm], $Pg/m, $Zn">;
-class sme_vector_to_tile_inst_Q<MatrixTileVectorOperand tile_ty,
- bit is_col, string mnemonic>
- : sme_vector_to_tile_base<0b1, is_col, 0b11, (outs tile_ty:$ZAd),
- (ins MatrixIndexGPR32Op12_15:$Rv, PPR3bAny:$Pg, ZPR128:$Zn),
- mnemonic, "\t$ZAd[$Rv], $Pg/m, $Zn">;
-
multiclass sme_vector_to_tile_aliases<Instruction inst,
MatrixTileVectorOperand tile_ty,
ZPRRegOp zpr_ty, Operand imm_ty> {
@@ -484,39 +440,39 @@ multiclass sme_vector_to_tile_aliases<Instruction inst,
}
multiclass sme_vector_v_to_tile<string mnemonic, bit is_col> {
- def _B : sme_vector_to_tile_inst<0b00, !if(is_col, TileVectorOpV8,
- TileVectorOpH8),
- is_col, imm0_15, ZPR8, mnemonic> {
+ def _B : sme_vector_to_tile_inst<0b0, 0b00, !if(is_col, TileVectorOpV8,
+ TileVectorOpH8),
+ is_col, sme_elm_idx0_15, ZPR8, mnemonic> {
bits<4> imm;
let Inst{3-0} = imm;
}
- def _H : sme_vector_to_tile_inst<0b01, !if(is_col, TileVectorOpV16,
- TileVectorOpH16),
- is_col, imm0_7, ZPR16, mnemonic> {
+ def _H : sme_vector_to_tile_inst<0b0, 0b01, !if(is_col, TileVectorOpV16,
+ TileVectorOpH16),
+ is_col, sme_elm_idx0_7, ZPR16, mnemonic> {
bits<1> ZAd;
bits<3> imm;
let Inst{3} = ZAd;
let Inst{2-0} = imm;
}
- def _S : sme_vector_to_tile_inst<0b10, !if(is_col, TileVectorOpV32,
- TileVectorOpH32),
- is_col, imm0_3, ZPR32, mnemonic> {
+ def _S : sme_vector_to_tile_inst<0b0, 0b10, !if(is_col, TileVectorOpV32,
+ TileVectorOpH32),
+ is_col, sme_elm_idx0_3, ZPR32, mnemonic> {
bits<2> ZAd;
bits<2> imm;
let Inst{3-2} = ZAd;
let Inst{1-0} = imm;
}
- def _D : sme_vector_to_tile_inst<0b11, !if(is_col, TileVectorOpV64,
- TileVectorOpH64),
- is_col, imm0_1, ZPR64, mnemonic> {
+ def _D : sme_vector_to_tile_inst<0b0, 0b11, !if(is_col, TileVectorOpV64,
+ TileVectorOpH64),
+ is_col, sme_elm_idx0_1, ZPR64, mnemonic> {
bits<3> ZAd;
bits<1> imm;
let Inst{3-1} = ZAd;
let Inst{0} = imm;
}
- def _Q : sme_vector_to_tile_inst_Q<!if(is_col, TileVectorOpV128,
- TileVectorOpH128),
- is_col, mnemonic> {
+ def _Q : sme_vector_to_tile_inst<0b1, 0b11, !if(is_col, TileVectorOpV128,
+ TileVectorOpH128),
+ is_col, sme_elm_idx0_0, ZPR128, mnemonic> {
bits<4> ZAd;
bits<1> imm;
let Inst{3-0} = ZAd;
@@ -525,26 +481,23 @@ multiclass sme_vector_v_to_tile<string mnemonic, bit is_col> {
defm : sme_vector_to_tile_aliases<!cast<Instruction>(NAME # _B),
!if(is_col, TileVectorOpV8,
TileVectorOpH8),
- ZPR8, imm0_15>;
+ ZPR8, sme_elm_idx0_15>;
defm : sme_vector_to_tile_aliases<!cast<Instruction>(NAME # _H),
!if(is_col, TileVectorOpV16,
TileVectorOpH16),
- ZPR16, imm0_7>;
+ ZPR16, sme_elm_idx0_7>;
defm : sme_vector_to_tile_aliases<!cast<Instruction>(NAME # _S),
!if(is_col, TileVectorOpV32,
TileVectorOpH32),
- ZPR32, imm0_3>;
+ ZPR32, sme_elm_idx0_3>;
defm : sme_vector_to_tile_aliases<!cast<Instruction>(NAME # _D),
!if(is_col, TileVectorOpV64,
TileVectorOpH64),
- ZPR64, imm0_1>;
-
- def : InstAlias<"mov\t$ZAd[$Rv], $Pg/m, $Zn",
- (!cast<Instruction>(NAME # _Q) !if(is_col,
- TileVectorOpV128,
- TileVectorOpH128):$ZAd,
- MatrixIndexGPR32Op12_15:$Rv,
- PPR3bAny:$Pg, ZPR128:$Zn), 1>;
+ ZPR64, sme_elm_idx0_1>;
+ defm : sme_vector_to_tile_aliases<!cast<Instruction>(NAME # _Q),
+ !if(is_col, TileVectorOpV128,
+ TileVectorOpH128),
+ ZPR128, sme_elm_idx0_0>;
}
multiclass sme_vector_to_tile<string mnemonic> {
@@ -569,19 +522,13 @@ class sme_tile_to_vector_base<bit Q, bit V, bits<2> sz, dag outs, dag ins,
let Inst{4-0} = Zd;
}
-class sme_tile_to_vector_inst<bits<2> sz, ZPRRegOp zpr_ty,
+class sme_tile_to_vector_inst<bit Q, bits<2> sz, ZPRRegOp zpr_ty,
MatrixTileVectorOperand tile_ty,
bit is_col, Operand imm_ty, string mnemonic>
- : sme_tile_to_vector_base<0b0, is_col, sz, (outs zpr_ty:$Zd),
+ : sme_tile_to_vector_base<Q, is_col, sz, (outs zpr_ty:$Zd),
(ins PPR3bAny:$Pg, tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm),
mnemonic, "\t$Zd, $Pg/m, $ZAn[$Rv, $imm]">;
-class sme_tile_to_vector_inst_Q<MatrixTileVectorOperand tile_ty,
- bit is_col, string mnemonic>
- : sme_tile_to_vector_base<0b1, is_col, 0b11, (outs ZPR128:$Zd),
- (ins PPR3bAny:$Pg, tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rv),
- mnemonic, "\t$Zd, $Pg/m, $ZAn[$Rv]">;
-
multiclass sme_tile_to_vector_aliases<Instruction inst, ZPRRegOp zpr_ty,
MatrixTileVectorOperand tile_ty,
Operand imm_ty > {
@@ -590,62 +537,58 @@ multiclass sme_tile_to_vector_aliases<Instruction inst, ZPRRegOp zpr_ty,
}
multiclass sme_tile_to_vector_v<string mnemonic, bit is_col> {
- def _B : sme_tile_to_vector_inst<0b00, ZPR8, !if(is_col, TileVectorOpV8,
- TileVectorOpH8),
- is_col, imm0_15, mnemonic> {
+ def _B : sme_tile_to_vector_inst<0b0, 0b00, ZPR8, !if(is_col, TileVectorOpV8,
+ TileVectorOpH8),
+ is_col, sme_elm_idx0_15, mnemonic> {
bits<4> imm;
let Inst{8-5} = imm;
}
- def _H : sme_tile_to_vector_inst<0b01, ZPR16, !if(is_col, TileVectorOpV16,
- TileVectorOpH16),
- is_col, imm0_7, mnemonic> {
+ def _H : sme_tile_to_vector_inst<0b0, 0b01, ZPR16, !if(is_col, TileVectorOpV16,
+ TileVectorOpH16),
+ is_col, sme_elm_idx0_7, mnemonic> {
bits<1> ZAn;
bits<3> imm;
let Inst{8} = ZAn;
let Inst{7-5} = imm;
}
- def _S : sme_tile_to_vector_inst<0b10, ZPR32, !if(is_col, TileVectorOpV32,
- TileVectorOpH32),
- is_col, imm0_3, mnemonic> {
+ def _S : sme_tile_to_vector_inst<0b0, 0b10, ZPR32, !if(is_col, TileVectorOpV32,
+ TileVectorOpH32),
+ is_col, sme_elm_idx0_3, mnemonic> {
bits<2> ZAn;
bits<2> imm;
let Inst{8-7} = ZAn;
let Inst{6-5} = imm;
}
- def _D : sme_tile_to_vector_inst<0b11, ZPR64, !if(is_col, TileVectorOpV64,
- TileVectorOpH64),
- is_col, imm0_1, mnemonic> {
+ def _D : sme_tile_to_vector_inst<0b0, 0b11, ZPR64, !if(is_col, TileVectorOpV64,
+ TileVectorOpH64),
+ is_col, sme_elm_idx0_1, mnemonic> {
bits<3> ZAn;
bits<1> imm;
let Inst{8-6} = ZAn;
let Inst{5} = imm;
}
- def _Q : sme_tile_to_vector_inst_Q<!if(is_col, TileVectorOpV128,
- TileVectorOpH128),
- is_col, mnemonic> {
+ def _Q : sme_tile_to_vector_inst<0b1, 0b11, ZPR128, !if(is_col, TileVectorOpV128,
+ TileVectorOpH128),
+ is_col, sme_elm_idx0_0, mnemonic> {
bits<4> ZAn;
let Inst{8-5} = ZAn;
}
defm : sme_tile_to_vector_aliases<!cast<Instruction>(NAME # _B), ZPR8,
!if(is_col, TileVectorOpV8,
- TileVectorOpH8), imm0_15>;
+ TileVectorOpH8), sme_elm_idx0_15>;
defm : sme_tile_to_vector_aliases<!cast<Instruction>(NAME # _H), ZPR16,
!if(is_col, TileVectorOpV16,
- TileVectorOpH16), imm0_7>;
+ TileVectorOpH16), sme_elm_idx0_7>;
defm : sme_tile_to_vector_aliases<!cast<Instruction>(NAME # _S), ZPR32,
!if(is_col, TileVectorOpV32,
- TileVectorOpH32), imm0_3>;
+ TileVectorOpH32), sme_elm_idx0_3>;
defm : sme_tile_to_vector_aliases<!cast<Instruction>(NAME # _D), ZPR64,
!if(is_col, TileVectorOpV64,
- TileVectorOpH64), imm0_1>;
-
- def : InstAlias<"mov\t$Zd, $Pg/m, $ZAn[$Rv]",
- (!cast<Instruction>(NAME # _Q) ZPR128:$Zd, PPR3bAny:$Pg,
- !if(is_col,
- TileVectorOpV128,
- TileVectorOpH128):$ZAn,
- MatrixIndexGPR32Op12_15:$Rv), 1>;
+ TileVectorOpH64), sme_elm_idx0_1>;
+ defm : sme_tile_to_vector_aliases<!cast<Instruction>(NAME # _Q), ZPR128,
+ !if(is_col, TileVectorOpV128,
+ TileVectorOpH128), sme_elm_idx0_0>;
}
multiclass sme_tile_to_vector<string mnemonic> {
diff --git a/llvm/test/MC/AArch64/SME/ld1b-diagnostics.s b/llvm/test/MC/AArch64/SME/ld1b-diagnostics.s
index b614c72211cfb..242cd1df739b3 100644
--- a/llvm/test/MC/AArch64/SME/ld1b-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/ld1b-diagnostics.s
@@ -3,32 +3,32 @@
// ------------------------------------------------------------------------- //
// Invalid tile (expected: za0h.b or za0v.b)
-ld1b {za1h.b[w12, #0]}, p0/z, [x0]
+ld1b {za1h.b[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: ld1b {za1h.b[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1b {za1h.b[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1b {za[w12, #0]}, p0/z, [x0]
+ld1b {za[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za0h.b or za0v.b
-// CHECK-NEXT: ld1b {za[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1b {za[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1b {za15v.q[w12, #0]}, p0/z, [x0]
+ld1b {za15v.q[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za0h.b or za0v.b
-// CHECK-NEXT: ld1b {za15v.q[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1b {za15v.q[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid vector select register (expected: w12-w15)
-ld1b {za0h.b[w11, #0]}, p0/z, [x0]
+ld1b {za0h.b[w11, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: ld1b {za0h.b[w11, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1b {za0h.b[w11, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1b {za0h.b[w16, #0]}, p0/z, [x0]
+ld1b {za0h.b[w16, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: ld1b {za0h.b[w16, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1b {za0h.b[w16, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
@@ -39,41 +39,41 @@ ld1b {za0h.b[w12]}, p0/z, [x0]
// CHECK-NEXT: ld1b {za0h.b[w12]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1b {za0h.b[w12, #16]}, p0/z, [x0]
+ld1b {za0h.b[w12, 16]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
-// CHECK-NEXT: ld1b {za0h.b[w12, #16]}, p0/z, [x0]
+// CHECK-NEXT: ld1b {za0h.b[w12, 16]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate (expected: p0-p7)
-ld1b {za0h.b[w12, #0]}, p8/z, [x0]
+ld1b {za0h.b[w12, 0]}, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
-// CHECK-NEXT: ld1b {za0h.b[w12, #0]}, p8/z, [x0]
+// CHECK-NEXT: ld1b {za0h.b[w12, 0]}, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate qualifier (expected: /z)
-ld1b {za0h.b[w12, #0]}, p0/m, [x0]
+ld1b {za0h.b[w12, 0]}, p0/m, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: ld1b {za0h.b[w12, #0]}, p0/m, [x0]
+// CHECK-NEXT: ld1b {za0h.b[w12, 0]}, p0/m, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid memory operands
-ld1b {za0h.b[w12, #0]}, p0/z, [w0]
+ld1b {za0h.b[w12, 0]}, p0/z, [w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: ld1b {za0h.b[w12, #0]}, p0/z, [w0]
+// CHECK-NEXT: ld1b {za0h.b[w12, 0]}, p0/z, [w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1b {za0h.b[w12, #0]}, p0/z, [x0, w0]
+ld1b {za0h.b[w12, 0]}, p0/z, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
-// CHECK-NEXT: ld1b {za0h.b[w12, #0]}, p0/z, [x0, w0]
+// CHECK-NEXT: ld1b {za0h.b[w12, 0]}, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1b {za0h.b[w12, #0]}, p0/z, [x0, x0, lsl #1]
+ld1b {za0h.b[w12, 0]}, p0/z, [x0, x0, lsl #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
-// CHECK-NEXT: ld1b {za0h.b[w12, #0]}, p0/z, [x0, x0, lsl #1]
+// CHECK-NEXT: ld1b {za0h.b[w12, 0]}, p0/z, [x0, x0, lsl #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/ld1b.s b/llvm/test/MC/AArch64/SME/ld1b.s
index cef0c66082631..85cac2c986a86 100644
--- a/llvm/test/MC/AArch64/SME/ld1b.s
+++ b/llvm/test/MC/AArch64/SME/ld1b.s
@@ -15,146 +15,146 @@
// --------------------------------------------------------------------------//
// Horizontal
-ld1b {za0h.b[w12, #0]}, p0/z, [x0, x0]
-// CHECK-INST: ld1b {za0h.b[w12, #0]}, p0/z, [x0, x0]
+ld1b {za0h.b[w12, 0]}, p0/z, [x0, x0]
+// CHECK-INST: ld1b {za0h.b[w12, 0]}, p0/z, [x0, x0]
// CHECK-ENCODING: [0x00,0x00,0x00,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 00 e0 <unknown>
-ld1b {za0h.b[w14, #5]}, p5/z, [x10, x21]
-// CHECK-INST: ld1b {za0h.b[w14, #5]}, p5/z, [x10, x21]
+ld1b {za0h.b[w14, 5]}, p5/z, [x10, x21]
+// CHECK-INST: ld1b {za0h.b[w14, 5]}, p5/z, [x10, x21]
// CHECK-ENCODING: [0x45,0x55,0x15,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 15 e0 <unknown>
-ld1b {za0h.b[w15, #7]}, p3/z, [x13, x8]
-// CHECK-INST: ld1b {za0h.b[w15, #7]}, p3/z, [x13, x8]
+ld1b {za0h.b[w15, 7]}, p3/z, [x13, x8]
+// CHECK-INST: ld1b {za0h.b[w15, 7]}, p3/z, [x13, x8]
// CHECK-ENCODING: [0xa7,0x6d,0x08,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 08 e0 <unknown>
-ld1b {za0h.b[w15, #15]}, p7/z, [sp]
-// CHECK-INST: ld1b {za0h.b[w15, #15]}, p7/z, [sp]
+ld1b {za0h.b[w15, 15]}, p7/z, [sp]
+// CHECK-INST: ld1b {za0h.b[w15, 15]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0x7f,0x1f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 1f e0 <unknown>
-ld1b {za0h.b[w12, #5]}, p3/z, [x17, x16]
-// CHECK-INST: ld1b {za0h.b[w12, #5]}, p3/z, [x17, x16]
+ld1b {za0h.b[w12, 5]}, p3/z, [x17, x16]
+// CHECK-INST: ld1b {za0h.b[w12, 5]}, p3/z, [x17, x16]
// CHECK-ENCODING: [0x25,0x0e,0x10,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 10 e0 <unknown>
-ld1b {za0h.b[w12, #1]}, p1/z, [x1, x30]
-// CHECK-INST: ld1b {za0h.b[w12, #1]}, p1/z, [x1, x30]
+ld1b {za0h.b[w12, 1]}, p1/z, [x1, x30]
+// CHECK-INST: ld1b {za0h.b[w12, 1]}, p1/z, [x1, x30]
// CHECK-ENCODING: [0x21,0x04,0x1e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 1e e0 <unknown>
-ld1b {za0h.b[w14, #8]}, p5/z, [x19, x20]
-// CHECK-INST: ld1b {za0h.b[w14, #8]}, p5/z, [x19, x20]
+ld1b {za0h.b[w14, 8]}, p5/z, [x19, x20]
+// CHECK-INST: ld1b {za0h.b[w14, 8]}, p5/z, [x19, x20]
// CHECK-ENCODING: [0x68,0x56,0x14,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 14 e0 <unknown>
-ld1b {za0h.b[w12, #0]}, p6/z, [x12, x2]
-// CHECK-INST: ld1b {za0h.b[w12, #0]}, p6/z, [x12, x2]
+ld1b {za0h.b[w12, 0]}, p6/z, [x12, x2]
+// CHECK-INST: ld1b {za0h.b[w12, 0]}, p6/z, [x12, x2]
// CHECK-ENCODING: [0x80,0x19,0x02,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 02 e0 <unknown>
-ld1b {za0h.b[w14, #1]}, p2/z, [x1, x26]
-// CHECK-INST: ld1b {za0h.b[w14, #1]}, p2/z, [x1, x26]
+ld1b {za0h.b[w14, 1]}, p2/z, [x1, x26]
+// CHECK-INST: ld1b {za0h.b[w14, 1]}, p2/z, [x1, x26]
// CHECK-ENCODING: [0x21,0x48,0x1a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 1a e0 <unknown>
-ld1b {za0h.b[w12, #13]}, p2/z, [x22, x30]
-// CHECK-INST: ld1b {za0h.b[w12, #13]}, p2/z, [x22, x30]
+ld1b {za0h.b[w12, 13]}, p2/z, [x22, x30]
+// CHECK-INST: ld1b {za0h.b[w12, 13]}, p2/z, [x22, x30]
// CHECK-ENCODING: [0xcd,0x0a,0x1e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 1e e0 <unknown>
-ld1b {za0h.b[w15, #2]}, p5/z, [x9, x1]
-// CHECK-INST: ld1b {za0h.b[w15, #2]}, p5/z, [x9, x1]
+ld1b {za0h.b[w15, 2]}, p5/z, [x9, x1]
+// CHECK-INST: ld1b {za0h.b[w15, 2]}, p5/z, [x9, x1]
// CHECK-ENCODING: [0x22,0x75,0x01,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 01 e0 <unknown>
-ld1b {za0h.b[w13, #7]}, p2/z, [x12, x11]
-// CHECK-INST: ld1b {za0h.b[w13, #7]}, p2/z, [x12, x11]
+ld1b {za0h.b[w13, 7]}, p2/z, [x12, x11]
+// CHECK-INST: ld1b {za0h.b[w13, 7]}, p2/z, [x12, x11]
// CHECK-ENCODING: [0x87,0x29,0x0b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 0b e0 <unknown>
-ld1b za0h.b[w12, #0], p0/z, [x0, x0]
-// CHECK-INST: ld1b {za0h.b[w12, #0]}, p0/z, [x0, x0]
+ld1b za0h.b[w12, 0], p0/z, [x0, x0]
+// CHECK-INST: ld1b {za0h.b[w12, 0]}, p0/z, [x0, x0]
// CHECK-ENCODING: [0x00,0x00,0x00,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 00 e0 <unknown>
-ld1b za0h.b[w14, #5], p5/z, [x10, x21]
-// CHECK-INST: ld1b {za0h.b[w14, #5]}, p5/z, [x10, x21]
+ld1b za0h.b[w14, 5], p5/z, [x10, x21]
+// CHECK-INST: ld1b {za0h.b[w14, 5]}, p5/z, [x10, x21]
// CHECK-ENCODING: [0x45,0x55,0x15,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 15 e0 <unknown>
-ld1b za0h.b[w15, #7], p3/z, [x13, x8]
-// CHECK-INST: ld1b {za0h.b[w15, #7]}, p3/z, [x13, x8]
+ld1b za0h.b[w15, 7], p3/z, [x13, x8]
+// CHECK-INST: ld1b {za0h.b[w15, 7]}, p3/z, [x13, x8]
// CHECK-ENCODING: [0xa7,0x6d,0x08,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 08 e0 <unknown>
-ld1b za0h.b[w15, #15], p7/z, [sp]
-// CHECK-INST: ld1b {za0h.b[w15, #15]}, p7/z, [sp]
+ld1b za0h.b[w15, 15], p7/z, [sp]
+// CHECK-INST: ld1b {za0h.b[w15, 15]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0x7f,0x1f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 1f e0 <unknown>
-ld1b za0h.b[w12, #5], p3/z, [x17, x16]
-// CHECK-INST: ld1b {za0h.b[w12, #5]}, p3/z, [x17, x16]
+ld1b za0h.b[w12, 5], p3/z, [x17, x16]
+// CHECK-INST: ld1b {za0h.b[w12, 5]}, p3/z, [x17, x16]
// CHECK-ENCODING: [0x25,0x0e,0x10,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 10 e0 <unknown>
-ld1b za0h.b[w12, #1], p1/z, [x1, x30]
-// CHECK-INST: ld1b {za0h.b[w12, #1]}, p1/z, [x1, x30]
+ld1b za0h.b[w12, 1], p1/z, [x1, x30]
+// CHECK-INST: ld1b {za0h.b[w12, 1]}, p1/z, [x1, x30]
// CHECK-ENCODING: [0x21,0x04,0x1e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 1e e0 <unknown>
-ld1b za0h.b[w14, #8], p5/z, [x19, x20]
-// CHECK-INST: ld1b {za0h.b[w14, #8]}, p5/z, [x19, x20]
+ld1b za0h.b[w14, 8], p5/z, [x19, x20]
+// CHECK-INST: ld1b {za0h.b[w14, 8]}, p5/z, [x19, x20]
// CHECK-ENCODING: [0x68,0x56,0x14,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 14 e0 <unknown>
-ld1b za0h.b[w12, #0], p6/z, [x12, x2]
-// CHECK-INST: ld1b {za0h.b[w12, #0]}, p6/z, [x12, x2]
+ld1b za0h.b[w12, 0], p6/z, [x12, x2]
+// CHECK-INST: ld1b {za0h.b[w12, 0]}, p6/z, [x12, x2]
// CHECK-ENCODING: [0x80,0x19,0x02,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 02 e0 <unknown>
-ld1b za0h.b[w14, #1], p2/z, [x1, x26]
-// CHECK-INST: ld1b {za0h.b[w14, #1]}, p2/z, [x1, x26]
+ld1b za0h.b[w14, 1], p2/z, [x1, x26]
+// CHECK-INST: ld1b {za0h.b[w14, 1]}, p2/z, [x1, x26]
// CHECK-ENCODING: [0x21,0x48,0x1a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 1a e0 <unknown>
-ld1b za0h.b[w12, #13], p2/z, [x22, x30]
-// CHECK-INST: ld1b {za0h.b[w12, #13]}, p2/z, [x22, x30]
+ld1b za0h.b[w12, 13], p2/z, [x22, x30]
+// CHECK-INST: ld1b {za0h.b[w12, 13]}, p2/z, [x22, x30]
// CHECK-ENCODING: [0xcd,0x0a,0x1e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 1e e0 <unknown>
-ld1b za0h.b[w15, #2], p5/z, [x9, x1]
-// CHECK-INST: ld1b {za0h.b[w15, #2]}, p5/z, [x9, x1]
+ld1b za0h.b[w15, 2], p5/z, [x9, x1]
+// CHECK-INST: ld1b {za0h.b[w15, 2]}, p5/z, [x9, x1]
// CHECK-ENCODING: [0x22,0x75,0x01,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 01 e0 <unknown>
-ld1b za0h.b[w13, #7], p2/z, [x12, x11]
-// CHECK-INST: ld1b {za0h.b[w13, #7]}, p2/z, [x12, x11]
+ld1b za0h.b[w13, 7], p2/z, [x12, x11]
+// CHECK-INST: ld1b {za0h.b[w13, 7]}, p2/z, [x12, x11]
// CHECK-ENCODING: [0x87,0x29,0x0b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 0b e0 <unknown>
@@ -162,146 +162,146 @@ ld1b za0h.b[w13, #7], p2/z, [x12, x11]
// --------------------------------------------------------------------------//
// Vertical
-ld1b {za0v.b[w12, #0]}, p0/z, [x0, x0]
-// CHECK-INST: ld1b {za0v.b[w12, #0]}, p0/z, [x0, x0]
+ld1b {za0v.b[w12, 0]}, p0/z, [x0, x0]
+// CHECK-INST: ld1b {za0v.b[w12, 0]}, p0/z, [x0, x0]
// CHECK-ENCODING: [0x00,0x80,0x00,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 00 e0 <unknown>
-ld1b {za0v.b[w14, #5]}, p5/z, [x10, x21]
-// CHECK-INST: ld1b {za0v.b[w14, #5]}, p5/z, [x10, x21]
+ld1b {za0v.b[w14, 5]}, p5/z, [x10, x21]
+// CHECK-INST: ld1b {za0v.b[w14, 5]}, p5/z, [x10, x21]
// CHECK-ENCODING: [0x45,0xd5,0x15,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 15 e0 <unknown>
-ld1b {za0v.b[w15, #7]}, p3/z, [x13, x8]
-// CHECK-INST: ld1b {za0v.b[w15, #7]}, p3/z, [x13, x8]
+ld1b {za0v.b[w15, 7]}, p3/z, [x13, x8]
+// CHECK-INST: ld1b {za0v.b[w15, 7]}, p3/z, [x13, x8]
// CHECK-ENCODING: [0xa7,0xed,0x08,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 08 e0 <unknown>
-ld1b {za0v.b[w15, #15]}, p7/z, [sp]
-// CHECK-INST: ld1b {za0v.b[w15, #15]}, p7/z, [sp]
+ld1b {za0v.b[w15, 15]}, p7/z, [sp]
+// CHECK-INST: ld1b {za0v.b[w15, 15]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0xff,0x1f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 1f e0 <unknown>
-ld1b {za0v.b[w12, #5]}, p3/z, [x17, x16]
-// CHECK-INST: ld1b {za0v.b[w12, #5]}, p3/z, [x17, x16]
+ld1b {za0v.b[w12, 5]}, p3/z, [x17, x16]
+// CHECK-INST: ld1b {za0v.b[w12, 5]}, p3/z, [x17, x16]
// CHECK-ENCODING: [0x25,0x8e,0x10,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 10 e0 <unknown>
-ld1b {za0v.b[w12, #1]}, p1/z, [x1, x30]
-// CHECK-INST: ld1b {za0v.b[w12, #1]}, p1/z, [x1, x30]
+ld1b {za0v.b[w12, 1]}, p1/z, [x1, x30]
+// CHECK-INST: ld1b {za0v.b[w12, 1]}, p1/z, [x1, x30]
// CHECK-ENCODING: [0x21,0x84,0x1e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 1e e0 <unknown>
-ld1b {za0v.b[w14, #8]}, p5/z, [x19, x20]
-// CHECK-INST: ld1b {za0v.b[w14, #8]}, p5/z, [x19, x20]
+ld1b {za0v.b[w14, 8]}, p5/z, [x19, x20]
+// CHECK-INST: ld1b {za0v.b[w14, 8]}, p5/z, [x19, x20]
// CHECK-ENCODING: [0x68,0xd6,0x14,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 14 e0 <unknown>
-ld1b {za0v.b[w12, #0]}, p6/z, [x12, x2]
-// CHECK-INST: ld1b {za0v.b[w12, #0]}, p6/z, [x12, x2]
+ld1b {za0v.b[w12, 0]}, p6/z, [x12, x2]
+// CHECK-INST: ld1b {za0v.b[w12, 0]}, p6/z, [x12, x2]
// CHECK-ENCODING: [0x80,0x99,0x02,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 02 e0 <unknown>
-ld1b {za0v.b[w14, #1]}, p2/z, [x1, x26]
-// CHECK-INST: ld1b {za0v.b[w14, #1]}, p2/z, [x1, x26]
+ld1b {za0v.b[w14, 1]}, p2/z, [x1, x26]
+// CHECK-INST: ld1b {za0v.b[w14, 1]}, p2/z, [x1, x26]
// CHECK-ENCODING: [0x21,0xc8,0x1a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 1a e0 <unknown>
-ld1b {za0v.b[w12, #13]}, p2/z, [x22, x30]
-// CHECK-INST: ld1b {za0v.b[w12, #13]}, p2/z, [x22, x30]
+ld1b {za0v.b[w12, 13]}, p2/z, [x22, x30]
+// CHECK-INST: ld1b {za0v.b[w12, 13]}, p2/z, [x22, x30]
// CHECK-ENCODING: [0xcd,0x8a,0x1e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 1e e0 <unknown>
-ld1b {za0v.b[w15, #2]}, p5/z, [x9, x1]
-// CHECK-INST: ld1b {za0v.b[w15, #2]}, p5/z, [x9, x1]
+ld1b {za0v.b[w15, 2]}, p5/z, [x9, x1]
+// CHECK-INST: ld1b {za0v.b[w15, 2]}, p5/z, [x9, x1]
// CHECK-ENCODING: [0x22,0xf5,0x01,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 01 e0 <unknown>
-ld1b {za0v.b[w13, #7]}, p2/z, [x12, x11]
-// CHECK-INST: ld1b {za0v.b[w13, #7]}, p2/z, [x12, x11]
+ld1b {za0v.b[w13, 7]}, p2/z, [x12, x11]
+// CHECK-INST: ld1b {za0v.b[w13, 7]}, p2/z, [x12, x11]
// CHECK-ENCODING: [0x87,0xa9,0x0b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 0b e0 <unknown>
-ld1b za0v.b[w12, #0], p0/z, [x0, x0]
-// CHECK-INST: ld1b {za0v.b[w12, #0]}, p0/z, [x0, x0]
+ld1b za0v.b[w12, 0], p0/z, [x0, x0]
+// CHECK-INST: ld1b {za0v.b[w12, 0]}, p0/z, [x0, x0]
// CHECK-ENCODING: [0x00,0x80,0x00,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 00 e0 <unknown>
-ld1b za0v.b[w14, #5], p5/z, [x10, x21]
-// CHECK-INST: ld1b {za0v.b[w14, #5]}, p5/z, [x10, x21]
+ld1b za0v.b[w14, 5], p5/z, [x10, x21]
+// CHECK-INST: ld1b {za0v.b[w14, 5]}, p5/z, [x10, x21]
// CHECK-ENCODING: [0x45,0xd5,0x15,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 15 e0 <unknown>
-ld1b za0v.b[w15, #7], p3/z, [x13, x8]
-// CHECK-INST: ld1b {za0v.b[w15, #7]}, p3/z, [x13, x8]
+ld1b za0v.b[w15, 7], p3/z, [x13, x8]
+// CHECK-INST: ld1b {za0v.b[w15, 7]}, p3/z, [x13, x8]
// CHECK-ENCODING: [0xa7,0xed,0x08,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 08 e0 <unknown>
-ld1b za0v.b[w15, #15], p7/z, [sp]
-// CHECK-INST: ld1b {za0v.b[w15, #15]}, p7/z, [sp]
+ld1b za0v.b[w15, 15], p7/z, [sp]
+// CHECK-INST: ld1b {za0v.b[w15, 15]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0xff,0x1f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 1f e0 <unknown>
-ld1b za0v.b[w12, #5], p3/z, [x17, x16]
-// CHECK-INST: ld1b {za0v.b[w12, #5]}, p3/z, [x17, x16]
+ld1b za0v.b[w12, 5], p3/z, [x17, x16]
+// CHECK-INST: ld1b {za0v.b[w12, 5]}, p3/z, [x17, x16]
// CHECK-ENCODING: [0x25,0x8e,0x10,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 10 e0 <unknown>
-ld1b za0v.b[w12, #1], p1/z, [x1, x30]
-// CHECK-INST: ld1b {za0v.b[w12, #1]}, p1/z, [x1, x30]
+ld1b za0v.b[w12, 1], p1/z, [x1, x30]
+// CHECK-INST: ld1b {za0v.b[w12, 1]}, p1/z, [x1, x30]
// CHECK-ENCODING: [0x21,0x84,0x1e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 1e e0 <unknown>
-ld1b za0v.b[w14, #8], p5/z, [x19, x20]
-// CHECK-INST: ld1b {za0v.b[w14, #8]}, p5/z, [x19, x20]
+ld1b za0v.b[w14, 8], p5/z, [x19, x20]
+// CHECK-INST: ld1b {za0v.b[w14, 8]}, p5/z, [x19, x20]
// CHECK-ENCODING: [0x68,0xd6,0x14,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 14 e0 <unknown>
-ld1b za0v.b[w12, #0], p6/z, [x12, x2]
-// CHECK-INST: ld1b {za0v.b[w12, #0]}, p6/z, [x12, x2]
+ld1b za0v.b[w12, 0], p6/z, [x12, x2]
+// CHECK-INST: ld1b {za0v.b[w12, 0]}, p6/z, [x12, x2]
// CHECK-ENCODING: [0x80,0x99,0x02,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 02 e0 <unknown>
-ld1b za0v.b[w14, #1], p2/z, [x1, x26]
-// CHECK-INST: ld1b {za0v.b[w14, #1]}, p2/z, [x1, x26]
+ld1b za0v.b[w14, 1], p2/z, [x1, x26]
+// CHECK-INST: ld1b {za0v.b[w14, 1]}, p2/z, [x1, x26]
// CHECK-ENCODING: [0x21,0xc8,0x1a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 1a e0 <unknown>
-ld1b za0v.b[w12, #13], p2/z, [x22, x30]
-// CHECK-INST: ld1b {za0v.b[w12, #13]}, p2/z, [x22, x30]
+ld1b za0v.b[w12, 13], p2/z, [x22, x30]
+// CHECK-INST: ld1b {za0v.b[w12, 13]}, p2/z, [x22, x30]
// CHECK-ENCODING: [0xcd,0x8a,0x1e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 1e e0 <unknown>
-ld1b za0v.b[w15, #2], p5/z, [x9, x1]
-// CHECK-INST: ld1b {za0v.b[w15, #2]}, p5/z, [x9, x1]
+ld1b za0v.b[w15, 2], p5/z, [x9, x1]
+// CHECK-INST: ld1b {za0v.b[w15, 2]}, p5/z, [x9, x1]
// CHECK-ENCODING: [0x22,0xf5,0x01,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 01 e0 <unknown>
-ld1b za0v.b[w13, #7], p2/z, [x12, x11]
-// CHECK-INST: ld1b {za0v.b[w13, #7]}, p2/z, [x12, x11]
+ld1b za0v.b[w13, 7], p2/z, [x12, x11]
+// CHECK-INST: ld1b {za0v.b[w13, 7]}, p2/z, [x12, x11]
// CHECK-ENCODING: [0x87,0xa9,0x0b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 0b e0 <unknown>
diff --git a/llvm/test/MC/AArch64/SME/ld1d-diagnostics.s b/llvm/test/MC/AArch64/SME/ld1d-diagnostics.s
index 00cbc2f404df0..ad3d85aa3a045 100644
--- a/llvm/test/MC/AArch64/SME/ld1d-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/ld1d-diagnostics.s
@@ -3,32 +3,32 @@
// ------------------------------------------------------------------------- //
// Invalid tile (expected: za[0-7]h.d or za[0-7]v.d)
-ld1d {za8h.d[w12, #0]}, p0/z, [x0]
+ld1d {za8h.d[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: ld1d {za8h.d[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1d {za8h.d[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1d {za[w12, #0]}, p0/z, [x0]
+ld1d {za[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-7]h.d or za[0-7]v.d
-// CHECK-NEXT: ld1d {za[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1d {za[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1d {za3h.s[w12, #0]}, p0/z, [x0]
+ld1d {za3h.s[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-7]h.d or za[0-7]v.d
-// CHECK-NEXT: ld1d {za3h.s[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1d {za3h.s[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid vector select register (expected: w12-w15)
-ld1d {za0h.d[w11, #0]}, p0/z, [x0]
+ld1d {za0h.d[w11, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: ld1d {za0h.d[w11, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1d {za0h.d[w11, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1d {za0h.d[w16, #0]}, p0/z, [x0]
+ld1d {za0h.d[w16, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: ld1d {za0h.d[w16, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1d {za0h.d[w16, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
@@ -39,41 +39,41 @@ ld1d {za0h.d[w12]}, p0/z, [x0]
// CHECK-NEXT: ld1d {za0h.d[w12]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1d {za0h.d[w12, #2]}, p0/z, [x0]
+ld1d {za0h.d[w12, 2]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
-// CHECK-NEXT: ld1d {za0h.d[w12, #2]}, p0/z, [x0]
+// CHECK-NEXT: ld1d {za0h.d[w12, 2]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate (expected: p0-p7)
-ld1d {za0h.d[w12, #0]}, p8/z, [x0]
+ld1d {za0h.d[w12, 0]}, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
-// CHECK-NEXT: ld1d {za0h.d[w12, #0]}, p8/z, [x0]
+// CHECK-NEXT: ld1d {za0h.d[w12, 0]}, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate qualifier (expected: /z)
-ld1d {za0h.d[w12, #0]}, p0/m, [x0]
+ld1d {za0h.d[w12, 0]}, p0/m, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: ld1d {za0h.d[w12, #0]}, p0/m, [x0]
+// CHECK-NEXT: ld1d {za0h.d[w12, 0]}, p0/m, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid memory operands
-ld1d {za0h.d[w12, #0]}, p0/z, [w0]
+ld1d {za0h.d[w12, 0]}, p0/z, [w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: ld1d {za0h.d[w12, #0]}, p0/z, [w0]
+// CHECK-NEXT: ld1d {za0h.d[w12, 0]}, p0/z, [w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1d {za0h.d[w12, #0]}, p0/z, [x0, w0]
+ld1d {za0h.d[w12, 0]}, p0/z, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
-// CHECK-NEXT: ld1d {za0h.d[w12, #0]}, p0/z, [x0, w0]
+// CHECK-NEXT: ld1d {za0h.d[w12, 0]}, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1d {za0h.d[w12, #0]}, p0/z, [x0, x0, lsl #4]
+ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
-// CHECK-NEXT: ld1d {za0h.d[w12, #0]}, p0/z, [x0, x0, lsl #4]
+// CHECK-NEXT: ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/ld1d.s b/llvm/test/MC/AArch64/SME/ld1d.s
index 28150489b1e00..ccbf2827b73c0 100644
--- a/llvm/test/MC/AArch64/SME/ld1d.s
+++ b/llvm/test/MC/AArch64/SME/ld1d.s
@@ -15,146 +15,146 @@
// --------------------------------------------------------------------------//
// Horizontal
-ld1d {za0h.d[w12, #0]}, p0/z, [x0, x0, lsl #3]
-// CHECK-INST: ld1d {za0h.d[w12, #0]}, p0/z, [x0, x0, lsl #3]
+ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
+// CHECK-INST: ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
// CHECK-ENCODING: [0x00,0x00,0xc0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 c0 e0 <unknown>
-ld1d {za2h.d[w14, #1]}, p5/z, [x10, x21, lsl #3]
-// CHECK-INST: ld1d {za2h.d[w14, #1]}, p5/z, [x10, x21, lsl #3]
+ld1d {za2h.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
+// CHECK-INST: ld1d {za2h.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
// CHECK-ENCODING: [0x45,0x55,0xd5,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 d5 e0 <unknown>
-ld1d {za3h.d[w15, #1]}, p3/z, [x13, x8, lsl #3]
-// CHECK-INST: ld1d {za3h.d[w15, #1]}, p3/z, [x13, x8, lsl #3]
+ld1d {za3h.d[w15, 1]}, p3/z, [x13, x8, lsl #3]
+// CHECK-INST: ld1d {za3h.d[w15, 1]}, p3/z, [x13, x8, lsl #3]
// CHECK-ENCODING: [0xa7,0x6d,0xc8,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d c8 e0 <unknown>
-ld1d {za7h.d[w15, #1]}, p7/z, [sp]
-// CHECK-INST: ld1d {za7h.d[w15, #1]}, p7/z, [sp]
+ld1d {za7h.d[w15, 1]}, p7/z, [sp]
+// CHECK-INST: ld1d {za7h.d[w15, 1]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0x7f,0xdf,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f df e0 <unknown>
-ld1d {za2h.d[w12, #1]}, p3/z, [x17, x16, lsl #3]
-// CHECK-INST: ld1d {za2h.d[w12, #1]}, p3/z, [x17, x16, lsl #3]
+ld1d {za2h.d[w12, 1]}, p3/z, [x17, x16, lsl #3]
+// CHECK-INST: ld1d {za2h.d[w12, 1]}, p3/z, [x17, x16, lsl #3]
// CHECK-ENCODING: [0x25,0x0e,0xd0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e d0 e0 <unknown>
-ld1d {za0h.d[w12, #1]}, p1/z, [x1, x30, lsl #3]
-// CHECK-INST: ld1d {za0h.d[w12, #1]}, p1/z, [x1, x30, lsl #3]
+ld1d {za0h.d[w12, 1]}, p1/z, [x1, x30, lsl #3]
+// CHECK-INST: ld1d {za0h.d[w12, 1]}, p1/z, [x1, x30, lsl #3]
// CHECK-ENCODING: [0x21,0x04,0xde,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 de e0 <unknown>
-ld1d {za4h.d[w14, #0]}, p5/z, [x19, x20, lsl #3]
-// CHECK-INST: ld1d {za4h.d[w14, #0]}, p5/z, [x19, x20, lsl #3]
+ld1d {za4h.d[w14, 0]}, p5/z, [x19, x20, lsl #3]
+// CHECK-INST: ld1d {za4h.d[w14, 0]}, p5/z, [x19, x20, lsl #3]
// CHECK-ENCODING: [0x68,0x56,0xd4,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 d4 e0 <unknown>
-ld1d {za0h.d[w12, #0]}, p6/z, [x12, x2, lsl #3]
-// CHECK-INST: ld1d {za0h.d[w12, #0]}, p6/z, [x12, x2, lsl #3]
+ld1d {za0h.d[w12, 0]}, p6/z, [x12, x2, lsl #3]
+// CHECK-INST: ld1d {za0h.d[w12, 0]}, p6/z, [x12, x2, lsl #3]
// CHECK-ENCODING: [0x80,0x19,0xc2,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 c2 e0 <unknown>
-ld1d {za0h.d[w14, #1]}, p2/z, [x1, x26, lsl #3]
-// CHECK-INST: ld1d {za0h.d[w14, #1]}, p2/z, [x1, x26, lsl #3]
+ld1d {za0h.d[w14, 1]}, p2/z, [x1, x26, lsl #3]
+// CHECK-INST: ld1d {za0h.d[w14, 1]}, p2/z, [x1, x26, lsl #3]
// CHECK-ENCODING: [0x21,0x48,0xda,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 da e0 <unknown>
-ld1d {za6h.d[w12, #1]}, p2/z, [x22, x30, lsl #3]
-// CHECK-INST: ld1d {za6h.d[w12, #1]}, p2/z, [x22, x30, lsl #3]
+ld1d {za6h.d[w12, 1]}, p2/z, [x22, x30, lsl #3]
+// CHECK-INST: ld1d {za6h.d[w12, 1]}, p2/z, [x22, x30, lsl #3]
// CHECK-ENCODING: [0xcd,0x0a,0xde,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a de e0 <unknown>
-ld1d {za1h.d[w15, #0]}, p5/z, [x9, x1, lsl #3]
-// CHECK-INST: ld1d {za1h.d[w15, #0]}, p5/z, [x9, x1, lsl #3]
+ld1d {za1h.d[w15, 0]}, p5/z, [x9, x1, lsl #3]
+// CHECK-INST: ld1d {za1h.d[w15, 0]}, p5/z, [x9, x1, lsl #3]
// CHECK-ENCODING: [0x22,0x75,0xc1,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 c1 e0 <unknown>
-ld1d {za3h.d[w13, #1]}, p2/z, [x12, x11, lsl #3]
-// CHECK-INST: ld1d {za3h.d[w13, #1]}, p2/z, [x12, x11, lsl #3]
+ld1d {za3h.d[w13, 1]}, p2/z, [x12, x11, lsl #3]
+// CHECK-INST: ld1d {za3h.d[w13, 1]}, p2/z, [x12, x11, lsl #3]
// CHECK-ENCODING: [0x87,0x29,0xcb,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 cb e0 <unknown>
-ld1d za0h.d[w12, #0], p0/z, [x0, x0, lsl #3]
-// CHECK-INST: ld1d {za0h.d[w12, #0]}, p0/z, [x0, x0, lsl #3]
+ld1d za0h.d[w12, 0], p0/z, [x0, x0, lsl #3]
+// CHECK-INST: ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
// CHECK-ENCODING: [0x00,0x00,0xc0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 c0 e0 <unknown>
-ld1d za2h.d[w14, #1], p5/z, [x10, x21, lsl #3]
-// CHECK-INST: ld1d {za2h.d[w14, #1]}, p5/z, [x10, x21, lsl #3]
+ld1d za2h.d[w14, 1], p5/z, [x10, x21, lsl #3]
+// CHECK-INST: ld1d {za2h.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
// CHECK-ENCODING: [0x45,0x55,0xd5,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 d5 e0 <unknown>
-ld1d za3h.d[w15, #1], p3/z, [x13, x8, lsl #3]
-// CHECK-INST: ld1d {za3h.d[w15, #1]}, p3/z, [x13, x8, lsl #3]
+ld1d za3h.d[w15, 1], p3/z, [x13, x8, lsl #3]
+// CHECK-INST: ld1d {za3h.d[w15, 1]}, p3/z, [x13, x8, lsl #3]
// CHECK-ENCODING: [0xa7,0x6d,0xc8,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d c8 e0 <unknown>
-ld1d za7h.d[w15, #1], p7/z, [sp]
-// CHECK-INST: ld1d {za7h.d[w15, #1]}, p7/z, [sp]
+ld1d za7h.d[w15, 1], p7/z, [sp]
+// CHECK-INST: ld1d {za7h.d[w15, 1]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0x7f,0xdf,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f df e0 <unknown>
-ld1d za2h.d[w12, #1], p3/z, [x17, x16, lsl #3]
-// CHECK-INST: ld1d {za2h.d[w12, #1]}, p3/z, [x17, x16, lsl #3]
+ld1d za2h.d[w12, 1], p3/z, [x17, x16, lsl #3]
+// CHECK-INST: ld1d {za2h.d[w12, 1]}, p3/z, [x17, x16, lsl #3]
// CHECK-ENCODING: [0x25,0x0e,0xd0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e d0 e0 <unknown>
-ld1d za0h.d[w12, #1], p1/z, [x1, x30, lsl #3]
-// CHECK-INST: ld1d {za0h.d[w12, #1]}, p1/z, [x1, x30, lsl #3]
+ld1d za0h.d[w12, 1], p1/z, [x1, x30, lsl #3]
+// CHECK-INST: ld1d {za0h.d[w12, 1]}, p1/z, [x1, x30, lsl #3]
// CHECK-ENCODING: [0x21,0x04,0xde,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 de e0 <unknown>
-ld1d za4h.d[w14, #0], p5/z, [x19, x20, lsl #3]
-// CHECK-INST: ld1d {za4h.d[w14, #0]}, p5/z, [x19, x20, lsl #3]
+ld1d za4h.d[w14, 0], p5/z, [x19, x20, lsl #3]
+// CHECK-INST: ld1d {za4h.d[w14, 0]}, p5/z, [x19, x20, lsl #3]
// CHECK-ENCODING: [0x68,0x56,0xd4,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 d4 e0 <unknown>
-ld1d za0h.d[w12, #0], p6/z, [x12, x2, lsl #3]
-// CHECK-INST: ld1d {za0h.d[w12, #0]}, p6/z, [x12, x2, lsl #3]
+ld1d za0h.d[w12, 0], p6/z, [x12, x2, lsl #3]
+// CHECK-INST: ld1d {za0h.d[w12, 0]}, p6/z, [x12, x2, lsl #3]
// CHECK-ENCODING: [0x80,0x19,0xc2,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 c2 e0 <unknown>
-ld1d za0h.d[w14, #1], p2/z, [x1, x26, lsl #3]
-// CHECK-INST: ld1d {za0h.d[w14, #1]}, p2/z, [x1, x26, lsl #3]
+ld1d za0h.d[w14, 1], p2/z, [x1, x26, lsl #3]
+// CHECK-INST: ld1d {za0h.d[w14, 1]}, p2/z, [x1, x26, lsl #3]
// CHECK-ENCODING: [0x21,0x48,0xda,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 da e0 <unknown>
-ld1d za6h.d[w12, #1], p2/z, [x22, x30, lsl #3]
-// CHECK-INST: ld1d {za6h.d[w12, #1]}, p2/z, [x22, x30, lsl #3]
+ld1d za6h.d[w12, 1], p2/z, [x22, x30, lsl #3]
+// CHECK-INST: ld1d {za6h.d[w12, 1]}, p2/z, [x22, x30, lsl #3]
// CHECK-ENCODING: [0xcd,0x0a,0xde,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a de e0 <unknown>
-ld1d za1h.d[w15, #0], p5/z, [x9, x1, lsl #3]
-// CHECK-INST: ld1d {za1h.d[w15, #0]}, p5/z, [x9, x1, lsl #3]
+ld1d za1h.d[w15, 0], p5/z, [x9, x1, lsl #3]
+// CHECK-INST: ld1d {za1h.d[w15, 0]}, p5/z, [x9, x1, lsl #3]
// CHECK-ENCODING: [0x22,0x75,0xc1,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 c1 e0 <unknown>
-ld1d za3h.d[w13, #1], p2/z, [x12, x11, lsl #3]
-// CHECK-INST: ld1d {za3h.d[w13, #1]}, p2/z, [x12, x11, lsl #3]
+ld1d za3h.d[w13, 1], p2/z, [x12, x11, lsl #3]
+// CHECK-INST: ld1d {za3h.d[w13, 1]}, p2/z, [x12, x11, lsl #3]
// CHECK-ENCODING: [0x87,0x29,0xcb,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 cb e0 <unknown>
@@ -162,146 +162,146 @@ ld1d za3h.d[w13, #1], p2/z, [x12, x11, lsl #3]
// --------------------------------------------------------------------------//
// Vertical
-ld1d {za0v.d[w12, #0]}, p0/z, [x0, x0, lsl #3]
-// CHECK-INST: ld1d {za0v.d[w12, #0]}, p0/z, [x0, x0, lsl #3]
+ld1d {za0v.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
+// CHECK-INST: ld1d {za0v.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
// CHECK-ENCODING: [0x00,0x80,0xc0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 c0 e0 <unknown>
-ld1d {za2v.d[w14, #1]}, p5/z, [x10, x21, lsl #3]
-// CHECK-INST: ld1d {za2v.d[w14, #1]}, p5/z, [x10, x21, lsl #3]
+ld1d {za2v.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
+// CHECK-INST: ld1d {za2v.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
// CHECK-ENCODING: [0x45,0xd5,0xd5,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 d5 e0 <unknown>
-ld1d {za3v.d[w15, #1]}, p3/z, [x13, x8, lsl #3]
-// CHECK-INST: ld1d {za3v.d[w15, #1]}, p3/z, [x13, x8, lsl #3]
+ld1d {za3v.d[w15, 1]}, p3/z, [x13, x8, lsl #3]
+// CHECK-INST: ld1d {za3v.d[w15, 1]}, p3/z, [x13, x8, lsl #3]
// CHECK-ENCODING: [0xa7,0xed,0xc8,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed c8 e0 <unknown>
-ld1d {za7v.d[w15, #1]}, p7/z, [sp]
-// CHECK-INST: ld1d {za7v.d[w15, #1]}, p7/z, [sp]
+ld1d {za7v.d[w15, 1]}, p7/z, [sp]
+// CHECK-INST: ld1d {za7v.d[w15, 1]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0xff,0xdf,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff df e0 <unknown>
-ld1d {za2v.d[w12, #1]}, p3/z, [x17, x16, lsl #3]
-// CHECK-INST: ld1d {za2v.d[w12, #1]}, p3/z, [x17, x16, lsl #3]
+ld1d {za2v.d[w12, 1]}, p3/z, [x17, x16, lsl #3]
+// CHECK-INST: ld1d {za2v.d[w12, 1]}, p3/z, [x17, x16, lsl #3]
// CHECK-ENCODING: [0x25,0x8e,0xd0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e d0 e0 <unknown>
-ld1d {za0v.d[w12, #1]}, p1/z, [x1, x30, lsl #3]
-// CHECK-INST: ld1d {za0v.d[w12, #1]}, p1/z, [x1, x30, lsl #3]
+ld1d {za0v.d[w12, 1]}, p1/z, [x1, x30, lsl #3]
+// CHECK-INST: ld1d {za0v.d[w12, 1]}, p1/z, [x1, x30, lsl #3]
// CHECK-ENCODING: [0x21,0x84,0xde,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 de e0 <unknown>
-ld1d {za4v.d[w14, #0]}, p5/z, [x19, x20, lsl #3]
-// CHECK-INST: ld1d {za4v.d[w14, #0]}, p5/z, [x19, x20, lsl #3]
+ld1d {za4v.d[w14, 0]}, p5/z, [x19, x20, lsl #3]
+// CHECK-INST: ld1d {za4v.d[w14, 0]}, p5/z, [x19, x20, lsl #3]
// CHECK-ENCODING: [0x68,0xd6,0xd4,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 d4 e0 <unknown>
-ld1d {za0v.d[w12, #0]}, p6/z, [x12, x2, lsl #3]
-// CHECK-INST: ld1d {za0v.d[w12, #0]}, p6/z, [x12, x2, lsl #3]
+ld1d {za0v.d[w12, 0]}, p6/z, [x12, x2, lsl #3]
+// CHECK-INST: ld1d {za0v.d[w12, 0]}, p6/z, [x12, x2, lsl #3]
// CHECK-ENCODING: [0x80,0x99,0xc2,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 c2 e0 <unknown>
-ld1d {za0v.d[w14, #1]}, p2/z, [x1, x26, lsl #3]
-// CHECK-INST: ld1d {za0v.d[w14, #1]}, p2/z, [x1, x26, lsl #3]
+ld1d {za0v.d[w14, 1]}, p2/z, [x1, x26, lsl #3]
+// CHECK-INST: ld1d {za0v.d[w14, 1]}, p2/z, [x1, x26, lsl #3]
// CHECK-ENCODING: [0x21,0xc8,0xda,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 da e0 <unknown>
-ld1d {za6v.d[w12, #1]}, p2/z, [x22, x30, lsl #3]
-// CHECK-INST: ld1d {za6v.d[w12, #1]}, p2/z, [x22, x30, lsl #3]
+ld1d {za6v.d[w12, 1]}, p2/z, [x22, x30, lsl #3]
+// CHECK-INST: ld1d {za6v.d[w12, 1]}, p2/z, [x22, x30, lsl #3]
// CHECK-ENCODING: [0xcd,0x8a,0xde,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a de e0 <unknown>
-ld1d {za1v.d[w15, #0]}, p5/z, [x9, x1, lsl #3]
-// CHECK-INST: ld1d {za1v.d[w15, #0]}, p5/z, [x9, x1, lsl #3]
+ld1d {za1v.d[w15, 0]}, p5/z, [x9, x1, lsl #3]
+// CHECK-INST: ld1d {za1v.d[w15, 0]}, p5/z, [x9, x1, lsl #3]
// CHECK-ENCODING: [0x22,0xf5,0xc1,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 c1 e0 <unknown>
-ld1d {za3v.d[w13, #1]}, p2/z, [x12, x11, lsl #3]
-// CHECK-INST: ld1d {za3v.d[w13, #1]}, p2/z, [x12, x11, lsl #3]
+ld1d {za3v.d[w13, 1]}, p2/z, [x12, x11, lsl #3]
+// CHECK-INST: ld1d {za3v.d[w13, 1]}, p2/z, [x12, x11, lsl #3]
// CHECK-ENCODING: [0x87,0xa9,0xcb,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 cb e0 <unknown>
-ld1d za0v.d[w12, #0], p0/z, [x0, x0, lsl #3]
-// CHECK-INST: ld1d {za0v.d[w12, #0]}, p0/z, [x0, x0, lsl #3]
+ld1d za0v.d[w12, 0], p0/z, [x0, x0, lsl #3]
+// CHECK-INST: ld1d {za0v.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
// CHECK-ENCODING: [0x00,0x80,0xc0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 c0 e0 <unknown>
-ld1d za2v.d[w14, #1], p5/z, [x10, x21, lsl #3]
-// CHECK-INST: ld1d {za2v.d[w14, #1]}, p5/z, [x10, x21, lsl #3]
+ld1d za2v.d[w14, 1], p5/z, [x10, x21, lsl #3]
+// CHECK-INST: ld1d {za2v.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
// CHECK-ENCODING: [0x45,0xd5,0xd5,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 d5 e0 <unknown>
-ld1d za3v.d[w15, #1], p3/z, [x13, x8, lsl #3]
-// CHECK-INST: ld1d {za3v.d[w15, #1]}, p3/z, [x13, x8, lsl #3]
+ld1d za3v.d[w15, 1], p3/z, [x13, x8, lsl #3]
+// CHECK-INST: ld1d {za3v.d[w15, 1]}, p3/z, [x13, x8, lsl #3]
// CHECK-ENCODING: [0xa7,0xed,0xc8,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed c8 e0 <unknown>
-ld1d za7v.d[w15, #1], p7/z, [sp]
-// CHECK-INST: ld1d {za7v.d[w15, #1]}, p7/z, [sp]
+ld1d za7v.d[w15, 1], p7/z, [sp]
+// CHECK-INST: ld1d {za7v.d[w15, 1]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0xff,0xdf,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff df e0 <unknown>
-ld1d za2v.d[w12, #1], p3/z, [x17, x16, lsl #3]
-// CHECK-INST: ld1d {za2v.d[w12, #1]}, p3/z, [x17, x16, lsl #3]
+ld1d za2v.d[w12, 1], p3/z, [x17, x16, lsl #3]
+// CHECK-INST: ld1d {za2v.d[w12, 1]}, p3/z, [x17, x16, lsl #3]
// CHECK-ENCODING: [0x25,0x8e,0xd0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e d0 e0 <unknown>
-ld1d za0v.d[w12, #1], p1/z, [x1, x30, lsl #3]
-// CHECK-INST: ld1d {za0v.d[w12, #1]}, p1/z, [x1, x30, lsl #3]
+ld1d za0v.d[w12, 1], p1/z, [x1, x30, lsl #3]
+// CHECK-INST: ld1d {za0v.d[w12, 1]}, p1/z, [x1, x30, lsl #3]
// CHECK-ENCODING: [0x21,0x84,0xde,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 de e0 <unknown>
-ld1d za4v.d[w14, #0], p5/z, [x19, x20, lsl #3]
-// CHECK-INST: ld1d {za4v.d[w14, #0]}, p5/z, [x19, x20, lsl #3]
+ld1d za4v.d[w14, 0], p5/z, [x19, x20, lsl #3]
+// CHECK-INST: ld1d {za4v.d[w14, 0]}, p5/z, [x19, x20, lsl #3]
// CHECK-ENCODING: [0x68,0xd6,0xd4,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 d4 e0 <unknown>
-ld1d za0v.d[w12, #0], p6/z, [x12, x2, lsl #3]
-// CHECK-INST: ld1d {za0v.d[w12, #0]}, p6/z, [x12, x2, lsl #3]
+ld1d za0v.d[w12, 0], p6/z, [x12, x2, lsl #3]
+// CHECK-INST: ld1d {za0v.d[w12, 0]}, p6/z, [x12, x2, lsl #3]
// CHECK-ENCODING: [0x80,0x99,0xc2,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 c2 e0 <unknown>
-ld1d za0v.d[w14, #1], p2/z, [x1, x26, lsl #3]
-// CHECK-INST: ld1d {za0v.d[w14, #1]}, p2/z, [x1, x26, lsl #3]
+ld1d za0v.d[w14, 1], p2/z, [x1, x26, lsl #3]
+// CHECK-INST: ld1d {za0v.d[w14, 1]}, p2/z, [x1, x26, lsl #3]
// CHECK-ENCODING: [0x21,0xc8,0xda,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 da e0 <unknown>
-ld1d za6v.d[w12, #1], p2/z, [x22, x30, lsl #3]
-// CHECK-INST: ld1d {za6v.d[w12, #1]}, p2/z, [x22, x30, lsl #3]
+ld1d za6v.d[w12, 1], p2/z, [x22, x30, lsl #3]
+// CHECK-INST: ld1d {za6v.d[w12, 1]}, p2/z, [x22, x30, lsl #3]
// CHECK-ENCODING: [0xcd,0x8a,0xde,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a de e0 <unknown>
-ld1d za1v.d[w15, #0], p5/z, [x9, x1, lsl #3]
-// CHECK-INST: ld1d {za1v.d[w15, #0]}, p5/z, [x9, x1, lsl #3]
+ld1d za1v.d[w15, 0], p5/z, [x9, x1, lsl #3]
+// CHECK-INST: ld1d {za1v.d[w15, 0]}, p5/z, [x9, x1, lsl #3]
// CHECK-ENCODING: [0x22,0xf5,0xc1,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 c1 e0 <unknown>
-ld1d za3v.d[w13, #1], p2/z, [x12, x11, lsl #3]
-// CHECK-INST: ld1d {za3v.d[w13, #1]}, p2/z, [x12, x11, lsl #3]
+ld1d za3v.d[w13, 1], p2/z, [x12, x11, lsl #3]
+// CHECK-INST: ld1d {za3v.d[w13, 1]}, p2/z, [x12, x11, lsl #3]
// CHECK-ENCODING: [0x87,0xa9,0xcb,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 cb e0 <unknown>
diff --git a/llvm/test/MC/AArch64/SME/ld1h-diagnostics.s b/llvm/test/MC/AArch64/SME/ld1h-diagnostics.s
index 679a14860a964..fd8849c3cb301 100644
--- a/llvm/test/MC/AArch64/SME/ld1h-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/ld1h-diagnostics.s
@@ -3,32 +3,32 @@
// ------------------------------------------------------------------------- //
// Invalid tile (expected: za[0-1]h.h or za[0-1]v.h)
-ld1h {za2h.h[w12, #0]}, p0/z, [x0]
+ld1h {za2h.h[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: ld1h {za2h.h[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1h {za2h.h[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1h {za[w12, #0]}, p0/z, [x0]
+ld1h {za[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-1]h.h or za[0-1]v.h
-// CHECK-NEXT: ld1h {za[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1h {za[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1h {za0.b[w12, #0]}, p0/z, [x0]
+ld1h {za0.b[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-1]h.h or za[0-1]v.h
-// CHECK-NEXT: ld1h {za0.b[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1h {za0.b[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid vector select register (expected: w12-w15)
-ld1h {za0h.h[w11, #0]}, p0/z, [x0]
+ld1h {za0h.h[w11, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: ld1h {za0h.h[w11, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1h {za0h.h[w11, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1h {za0h.h[w16, #0]}, p0/z, [x0]
+ld1h {za0h.h[w16, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: ld1h {za0h.h[w16, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1h {za0h.h[w16, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
@@ -39,41 +39,41 @@ ld1h {za0h.h[w12]}, p0/z, [x0]
// CHECK-NEXT: ld1h {za0h.h[w12]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1h {za0h.h[w12, #8]}, p0/z, [x0]
+ld1h {za0h.h[w12, 8]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
-// CHECK-NEXT: ld1h {za0h.h[w12, #8]}, p0/z, [x0]
+// CHECK-NEXT: ld1h {za0h.h[w12, 8]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate (expected: p0-p7)
-ld1h {za0h.h[w12, #0]}, p8/z, [x0]
+ld1h {za0h.h[w12, 0]}, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
-// CHECK-NEXT: ld1h {za0h.h[w12, #0]}, p8/z, [x0]
+// CHECK-NEXT: ld1h {za0h.h[w12, 0]}, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate qualifier (expected: /z)
-ld1h {za0h.h[w12, #0]}, p0/m, [x0]
+ld1h {za0h.h[w12, 0]}, p0/m, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: ld1h {za0h.h[w12, #0]}, p0/m, [x0]
+// CHECK-NEXT: ld1h {za0h.h[w12, 0]}, p0/m, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid memory operands
-ld1h {za0h.h[w12, #0]}, p0/z, [w0]
+ld1h {za0h.h[w12, 0]}, p0/z, [w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: ld1h {za0h.h[w12, #0]}, p0/z, [w0]
+// CHECK-NEXT: ld1h {za0h.h[w12, 0]}, p0/z, [w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1h {za0h.h[w12, #0]}, p0/z, [x0, w0]
+ld1h {za0h.h[w12, 0]}, p0/z, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
-// CHECK-NEXT: ld1h {za0h.h[w12, #0]}, p0/z, [x0, w0]
+// CHECK-NEXT: ld1h {za0h.h[w12, 0]}, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1h {za0h.h[w12, #0]}, p0/z, [x0, x0, lsl #2]
+ld1h {za0h.h[w12, 0]}, p0/z, [x0, x0, lsl #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
-// CHECK-NEXT: ld1h {za0h.h[w12, #0]}, p0/z, [x0, x0, lsl #2]
+// CHECK-NEXT: ld1h {za0h.h[w12, 0]}, p0/z, [x0, x0, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/ld1h.s b/llvm/test/MC/AArch64/SME/ld1h.s
index f5bd3c3f3ed6d..ef1673003f1c4 100644
--- a/llvm/test/MC/AArch64/SME/ld1h.s
+++ b/llvm/test/MC/AArch64/SME/ld1h.s
@@ -15,146 +15,146 @@
// --------------------------------------------------------------------------//
// Horizontal
-ld1h {za0h.h[w12, #0]}, p0/z, [x0, x0, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w12, #0]}, p0/z, [x0, x0, lsl #1]
+ld1h {za0h.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
// CHECK-ENCODING: [0x00,0x00,0x40,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 40 e0 <unknown>
-ld1h {za0h.h[w14, #5]}, p5/z, [x10, x21, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w14, #5]}, p5/z, [x10, x21, lsl #1]
+ld1h {za0h.h[w14, 5]}, p5/z, [x10, x21, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w14, 5]}, p5/z, [x10, x21, lsl #1]
// CHECK-ENCODING: [0x45,0x55,0x55,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 55 e0 <unknown>
-ld1h {za0h.h[w15, #7]}, p3/z, [x13, x8, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w15, #7]}, p3/z, [x13, x8, lsl #1]
+ld1h {za0h.h[w15, 7]}, p3/z, [x13, x8, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w15, 7]}, p3/z, [x13, x8, lsl #1]
// CHECK-ENCODING: [0xa7,0x6d,0x48,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 48 e0 <unknown>
-ld1h {za1h.h[w15, #7]}, p7/z, [sp]
-// CHECK-INST: ld1h {za1h.h[w15, #7]}, p7/z, [sp]
+ld1h {za1h.h[w15, 7]}, p7/z, [sp]
+// CHECK-INST: ld1h {za1h.h[w15, 7]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0x7f,0x5f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 5f e0 <unknown>
-ld1h {za0h.h[w12, #5]}, p3/z, [x17, x16, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w12, #5]}, p3/z, [x17, x16, lsl #1]
+ld1h {za0h.h[w12, 5]}, p3/z, [x17, x16, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w12, 5]}, p3/z, [x17, x16, lsl #1]
// CHECK-ENCODING: [0x25,0x0e,0x50,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 50 e0 <unknown>
-ld1h {za0h.h[w12, #1]}, p1/z, [x1, x30, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w12, #1]}, p1/z, [x1, x30, lsl #1]
+ld1h {za0h.h[w12, 1]}, p1/z, [x1, x30, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w12, 1]}, p1/z, [x1, x30, lsl #1]
// CHECK-ENCODING: [0x21,0x04,0x5e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 5e e0 <unknown>
-ld1h {za1h.h[w14, #0]}, p5/z, [x19, x20, lsl #1]
-// CHECK-INST: ld1h {za1h.h[w14, #0]}, p5/z, [x19, x20, lsl #1]
+ld1h {za1h.h[w14, 0]}, p5/z, [x19, x20, lsl #1]
+// CHECK-INST: ld1h {za1h.h[w14, 0]}, p5/z, [x19, x20, lsl #1]
// CHECK-ENCODING: [0x68,0x56,0x54,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 54 e0 <unknown>
-ld1h {za0h.h[w12, #0]}, p6/z, [x12, x2, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w12, #0]}, p6/z, [x12, x2, lsl #1]
+ld1h {za0h.h[w12, 0]}, p6/z, [x12, x2, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w12, 0]}, p6/z, [x12, x2, lsl #1]
// CHECK-ENCODING: [0x80,0x19,0x42,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 42 e0 <unknown>
-ld1h {za0h.h[w14, #1]}, p2/z, [x1, x26, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w14, #1]}, p2/z, [x1, x26, lsl #1]
+ld1h {za0h.h[w14, 1]}, p2/z, [x1, x26, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w14, 1]}, p2/z, [x1, x26, lsl #1]
// CHECK-ENCODING: [0x21,0x48,0x5a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 5a e0 <unknown>
-ld1h {za1h.h[w12, #5]}, p2/z, [x22, x30, lsl #1]
-// CHECK-INST: ld1h {za1h.h[w12, #5]}, p2/z, [x22, x30, lsl #1]
+ld1h {za1h.h[w12, 5]}, p2/z, [x22, x30, lsl #1]
+// CHECK-INST: ld1h {za1h.h[w12, 5]}, p2/z, [x22, x30, lsl #1]
// CHECK-ENCODING: [0xcd,0x0a,0x5e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 5e e0 <unknown>
-ld1h {za0h.h[w15, #2]}, p5/z, [x9, x1, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w15, #2]}, p5/z, [x9, x1, lsl #1]
+ld1h {za0h.h[w15, 2]}, p5/z, [x9, x1, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w15, 2]}, p5/z, [x9, x1, lsl #1]
// CHECK-ENCODING: [0x22,0x75,0x41,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 41 e0 <unknown>
-ld1h {za0h.h[w13, #7]}, p2/z, [x12, x11, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w13, #7]}, p2/z, [x12, x11, lsl #1]
+ld1h {za0h.h[w13, 7]}, p2/z, [x12, x11, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w13, 7]}, p2/z, [x12, x11, lsl #1]
// CHECK-ENCODING: [0x87,0x29,0x4b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 4b e0 <unknown>
-ld1h za0h.h[w12, #0], p0/z, [x0, x0, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w12, #0]}, p0/z, [x0, x0, lsl #1]
+ld1h za0h.h[w12, 0], p0/z, [x0, x0, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
// CHECK-ENCODING: [0x00,0x00,0x40,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 40 e0 <unknown>
-ld1h za0h.h[w14, #5], p5/z, [x10, x21, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w14, #5]}, p5/z, [x10, x21, lsl #1]
+ld1h za0h.h[w14, 5], p5/z, [x10, x21, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w14, 5]}, p5/z, [x10, x21, lsl #1]
// CHECK-ENCODING: [0x45,0x55,0x55,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 55 e0 <unknown>
-ld1h za0h.h[w15, #7], p3/z, [x13, x8, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w15, #7]}, p3/z, [x13, x8, lsl #1]
+ld1h za0h.h[w15, 7], p3/z, [x13, x8, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w15, 7]}, p3/z, [x13, x8, lsl #1]
// CHECK-ENCODING: [0xa7,0x6d,0x48,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 48 e0 <unknown>
-ld1h za1h.h[w15, #7], p7/z, [sp]
-// CHECK-INST: ld1h {za1h.h[w15, #7]}, p7/z, [sp]
+ld1h za1h.h[w15, 7], p7/z, [sp]
+// CHECK-INST: ld1h {za1h.h[w15, 7]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0x7f,0x5f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 5f e0 <unknown>
-ld1h za0h.h[w12, #5], p3/z, [x17, x16, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w12, #5]}, p3/z, [x17, x16, lsl #1]
+ld1h za0h.h[w12, 5], p3/z, [x17, x16, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w12, 5]}, p3/z, [x17, x16, lsl #1]
// CHECK-ENCODING: [0x25,0x0e,0x50,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 50 e0 <unknown>
-ld1h za0h.h[w12, #1], p1/z, [x1, x30, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w12, #1]}, p1/z, [x1, x30, lsl #1]
+ld1h za0h.h[w12, 1], p1/z, [x1, x30, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w12, 1]}, p1/z, [x1, x30, lsl #1]
// CHECK-ENCODING: [0x21,0x04,0x5e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 5e e0 <unknown>
-ld1h za1h.h[w14, #0], p5/z, [x19, x20, lsl #1]
-// CHECK-INST: ld1h {za1h.h[w14, #0]}, p5/z, [x19, x20, lsl #1]
+ld1h za1h.h[w14, 0], p5/z, [x19, x20, lsl #1]
+// CHECK-INST: ld1h {za1h.h[w14, 0]}, p5/z, [x19, x20, lsl #1]
// CHECK-ENCODING: [0x68,0x56,0x54,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 54 e0 <unknown>
-ld1h za0h.h[w12, #0], p6/z, [x12, x2, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w12, #0]}, p6/z, [x12, x2, lsl #1]
+ld1h za0h.h[w12, 0], p6/z, [x12, x2, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w12, 0]}, p6/z, [x12, x2, lsl #1]
// CHECK-ENCODING: [0x80,0x19,0x42,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 42 e0 <unknown>
-ld1h za0h.h[w14, #1], p2/z, [x1, x26, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w14, #1]}, p2/z, [x1, x26, lsl #1]
+ld1h za0h.h[w14, 1], p2/z, [x1, x26, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w14, 1]}, p2/z, [x1, x26, lsl #1]
// CHECK-ENCODING: [0x21,0x48,0x5a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 5a e0 <unknown>
-ld1h za1h.h[w12, #5], p2/z, [x22, x30, lsl #1]
-// CHECK-INST: ld1h {za1h.h[w12, #5]}, p2/z, [x22, x30, lsl #1]
+ld1h za1h.h[w12, 5], p2/z, [x22, x30, lsl #1]
+// CHECK-INST: ld1h {za1h.h[w12, 5]}, p2/z, [x22, x30, lsl #1]
// CHECK-ENCODING: [0xcd,0x0a,0x5e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 5e e0 <unknown>
-ld1h za0h.h[w15, #2], p5/z, [x9, x1, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w15, #2]}, p5/z, [x9, x1, lsl #1]
+ld1h za0h.h[w15, 2], p5/z, [x9, x1, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w15, 2]}, p5/z, [x9, x1, lsl #1]
// CHECK-ENCODING: [0x22,0x75,0x41,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 41 e0 <unknown>
-ld1h za0h.h[w13, #7], p2/z, [x12, x11, lsl #1]
-// CHECK-INST: ld1h {za0h.h[w13, #7]}, p2/z, [x12, x11, lsl #1]
+ld1h za0h.h[w13, 7], p2/z, [x12, x11, lsl #1]
+// CHECK-INST: ld1h {za0h.h[w13, 7]}, p2/z, [x12, x11, lsl #1]
// CHECK-ENCODING: [0x87,0x29,0x4b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 4b e0 <unknown>
@@ -162,146 +162,146 @@ ld1h za0h.h[w13, #7], p2/z, [x12, x11, lsl #1]
// --------------------------------------------------------------------------//
// Vertical
-ld1h {za0v.h[w12, #0]}, p0/z, [x0, x0, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w12, #0]}, p0/z, [x0, x0, lsl #1]
+ld1h {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
// CHECK-ENCODING: [0x00,0x80,0x40,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 40 e0 <unknown>
-ld1h {za0v.h[w14, #5]}, p5/z, [x10, x21, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w14, #5]}, p5/z, [x10, x21, lsl #1]
+ld1h {za0v.h[w14, 5]}, p5/z, [x10, x21, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w14, 5]}, p5/z, [x10, x21, lsl #1]
// CHECK-ENCODING: [0x45,0xd5,0x55,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 55 e0 <unknown>
-ld1h {za0v.h[w15, #7]}, p3/z, [x13, x8, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w15, #7]}, p3/z, [x13, x8, lsl #1]
+ld1h {za0v.h[w15, 7]}, p3/z, [x13, x8, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w15, 7]}, p3/z, [x13, x8, lsl #1]
// CHECK-ENCODING: [0xa7,0xed,0x48,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 48 e0 <unknown>
-ld1h {za1v.h[w15, #7]}, p7/z, [sp]
-// CHECK-INST: ld1h {za1v.h[w15, #7]}, p7/z, [sp]
+ld1h {za1v.h[w15, 7]}, p7/z, [sp]
+// CHECK-INST: ld1h {za1v.h[w15, 7]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0xff,0x5f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 5f e0 <unknown>
-ld1h {za0v.h[w12, #5]}, p3/z, [x17, x16, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w12, #5]}, p3/z, [x17, x16, lsl #1]
+ld1h {za0v.h[w12, 5]}, p3/z, [x17, x16, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w12, 5]}, p3/z, [x17, x16, lsl #1]
// CHECK-ENCODING: [0x25,0x8e,0x50,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 50 e0 <unknown>
-ld1h {za0v.h[w12, #1]}, p1/z, [x1, x30, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w12, #1]}, p1/z, [x1, x30, lsl #1]
+ld1h {za0v.h[w12, 1]}, p1/z, [x1, x30, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w12, 1]}, p1/z, [x1, x30, lsl #1]
// CHECK-ENCODING: [0x21,0x84,0x5e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 5e e0 <unknown>
-ld1h {za1v.h[w14, #0]}, p5/z, [x19, x20, lsl #1]
-// CHECK-INST: ld1h {za1v.h[w14, #0]}, p5/z, [x19, x20, lsl #1]
+ld1h {za1v.h[w14, 0]}, p5/z, [x19, x20, lsl #1]
+// CHECK-INST: ld1h {za1v.h[w14, 0]}, p5/z, [x19, x20, lsl #1]
// CHECK-ENCODING: [0x68,0xd6,0x54,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 54 e0 <unknown>
-ld1h {za0v.h[w12, #0]}, p6/z, [x12, x2, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w12, #0]}, p6/z, [x12, x2, lsl #1]
+ld1h {za0v.h[w12, 0]}, p6/z, [x12, x2, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w12, 0]}, p6/z, [x12, x2, lsl #1]
// CHECK-ENCODING: [0x80,0x99,0x42,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 42 e0 <unknown>
-ld1h {za0v.h[w14, #1]}, p2/z, [x1, x26, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w14, #1]}, p2/z, [x1, x26, lsl #1]
+ld1h {za0v.h[w14, 1]}, p2/z, [x1, x26, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w14, 1]}, p2/z, [x1, x26, lsl #1]
// CHECK-ENCODING: [0x21,0xc8,0x5a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 5a e0 <unknown>
-ld1h {za1v.h[w12, #5]}, p2/z, [x22, x30, lsl #1]
-// CHECK-INST: ld1h {za1v.h[w12, #5]}, p2/z, [x22, x30, lsl #1]
+ld1h {za1v.h[w12, 5]}, p2/z, [x22, x30, lsl #1]
+// CHECK-INST: ld1h {za1v.h[w12, 5]}, p2/z, [x22, x30, lsl #1]
// CHECK-ENCODING: [0xcd,0x8a,0x5e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 5e e0 <unknown>
-ld1h {za0v.h[w15, #2]}, p5/z, [x9, x1, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w15, #2]}, p5/z, [x9, x1, lsl #1]
+ld1h {za0v.h[w15, 2]}, p5/z, [x9, x1, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w15, 2]}, p5/z, [x9, x1, lsl #1]
// CHECK-ENCODING: [0x22,0xf5,0x41,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 41 e0 <unknown>
-ld1h {za0v.h[w13, #7]}, p2/z, [x12, x11, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w13, #7]}, p2/z, [x12, x11, lsl #1]
+ld1h {za0v.h[w13, 7]}, p2/z, [x12, x11, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w13, 7]}, p2/z, [x12, x11, lsl #1]
// CHECK-ENCODING: [0x87,0xa9,0x4b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 4b e0 <unknown>
-ld1h za0v.h[w12, #0], p0/z, [x0, x0, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w12, #0]}, p0/z, [x0, x0, lsl #1]
+ld1h za0v.h[w12, 0], p0/z, [x0, x0, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
// CHECK-ENCODING: [0x00,0x80,0x40,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 40 e0 <unknown>
-ld1h za0v.h[w14, #5], p5/z, [x10, x21, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w14, #5]}, p5/z, [x10, x21, lsl #1]
+ld1h za0v.h[w14, 5], p5/z, [x10, x21, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w14, 5]}, p5/z, [x10, x21, lsl #1]
// CHECK-ENCODING: [0x45,0xd5,0x55,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 55 e0 <unknown>
-ld1h za0v.h[w15, #7], p3/z, [x13, x8, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w15, #7]}, p3/z, [x13, x8, lsl #1]
+ld1h za0v.h[w15, 7], p3/z, [x13, x8, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w15, 7]}, p3/z, [x13, x8, lsl #1]
// CHECK-ENCODING: [0xa7,0xed,0x48,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 48 e0 <unknown>
-ld1h za1v.h[w15, #7], p7/z, [sp]
-// CHECK-INST: ld1h {za1v.h[w15, #7]}, p7/z, [sp]
+ld1h za1v.h[w15, 7], p7/z, [sp]
+// CHECK-INST: ld1h {za1v.h[w15, 7]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0xff,0x5f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 5f e0 <unknown>
-ld1h za0v.h[w12, #5], p3/z, [x17, x16, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w12, #5]}, p3/z, [x17, x16, lsl #1]
+ld1h za0v.h[w12, 5], p3/z, [x17, x16, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w12, 5]}, p3/z, [x17, x16, lsl #1]
// CHECK-ENCODING: [0x25,0x8e,0x50,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 50 e0 <unknown>
-ld1h za0v.h[w12, #1], p1/z, [x1, x30, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w12, #1]}, p1/z, [x1, x30, lsl #1]
+ld1h za0v.h[w12, 1], p1/z, [x1, x30, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w12, 1]}, p1/z, [x1, x30, lsl #1]
// CHECK-ENCODING: [0x21,0x84,0x5e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 5e e0 <unknown>
-ld1h za1v.h[w14, #0], p5/z, [x19, x20, lsl #1]
-// CHECK-INST: ld1h {za1v.h[w14, #0]}, p5/z, [x19, x20, lsl #1]
+ld1h za1v.h[w14, 0], p5/z, [x19, x20, lsl #1]
+// CHECK-INST: ld1h {za1v.h[w14, 0]}, p5/z, [x19, x20, lsl #1]
// CHECK-ENCODING: [0x68,0xd6,0x54,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 54 e0 <unknown>
-ld1h za0v.h[w12, #0], p6/z, [x12, x2, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w12, #0]}, p6/z, [x12, x2, lsl #1]
+ld1h za0v.h[w12, 0], p6/z, [x12, x2, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w12, 0]}, p6/z, [x12, x2, lsl #1]
// CHECK-ENCODING: [0x80,0x99,0x42,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 42 e0 <unknown>
-ld1h za0v.h[w14, #1], p2/z, [x1, x26, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w14, #1]}, p2/z, [x1, x26, lsl #1]
+ld1h za0v.h[w14, 1], p2/z, [x1, x26, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w14, 1]}, p2/z, [x1, x26, lsl #1]
// CHECK-ENCODING: [0x21,0xc8,0x5a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 5a e0 <unknown>
-ld1h za1v.h[w12, #5], p2/z, [x22, x30, lsl #1]
-// CHECK-INST: ld1h {za1v.h[w12, #5]}, p2/z, [x22, x30, lsl #1]
+ld1h za1v.h[w12, 5], p2/z, [x22, x30, lsl #1]
+// CHECK-INST: ld1h {za1v.h[w12, 5]}, p2/z, [x22, x30, lsl #1]
// CHECK-ENCODING: [0xcd,0x8a,0x5e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 5e e0 <unknown>
-ld1h za0v.h[w15, #2], p5/z, [x9, x1, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w15, #2]}, p5/z, [x9, x1, lsl #1]
+ld1h za0v.h[w15, 2], p5/z, [x9, x1, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w15, 2]}, p5/z, [x9, x1, lsl #1]
// CHECK-ENCODING: [0x22,0xf5,0x41,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 41 e0 <unknown>
-ld1h za0v.h[w13, #7], p2/z, [x12, x11, lsl #1]
-// CHECK-INST: ld1h {za0v.h[w13, #7]}, p2/z, [x12, x11, lsl #1]
+ld1h za0v.h[w13, 7], p2/z, [x12, x11, lsl #1]
+// CHECK-INST: ld1h {za0v.h[w13, 7]}, p2/z, [x12, x11, lsl #1]
// CHECK-ENCODING: [0x87,0xa9,0x4b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 4b e0 <unknown>
diff --git a/llvm/test/MC/AArch64/SME/ld1q-diagnostics.s b/llvm/test/MC/AArch64/SME/ld1q-diagnostics.s
index 06cf153db6ae5..654d7b1038375 100644
--- a/llvm/test/MC/AArch64/SME/ld1q-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/ld1q-diagnostics.s
@@ -3,64 +3,77 @@
// ------------------------------------------------------------------------- //
// Invalid tile (expected: za[0-15]h.q or za[0-15]v.q)
-ld1q {za16h.q[w12]}, p0/z, [x0]
+ld1q {za16h.q[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: ld1q {za16h.q[w12]}, p0/z, [x0]
+// CHECK-NEXT: ld1q {za16h.q[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1q {za[w12]}, p0/z, [x0]
+ld1q {za[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-15]h.q or za[0-15]v.q
-// CHECK-NEXT: ld1q {za[w12]}, p0/z, [x0]
+// CHECK-NEXT: ld1q {za[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1q {za7v.d[w12]}, p0/z, [x0]
+ld1q {za7v.d[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-15]h.q or za[0-15]v.q
-// CHECK-NEXT: ld1q {za7v.d[w12]}, p0/z, [x0]
+// CHECK-NEXT: ld1q {za7v.d[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid vector select register (expected: w12-w15)
-ld1q {za0h.q[w11]}, p0/z, [x0]
+ld1q {za0h.q[w11, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: ld1q {za0h.q[w11]}, p0/z, [x0]
+// CHECK-NEXT: ld1q {za0h.q[w11, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1q {za0h.q[w16]}, p0/z, [x0]
+ld1q {za0h.q[w16, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: ld1q {za0h.q[w16]}, p0/z, [x0]
+// CHECK-NEXT: ld1q {za0h.q[w16, 0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select offset (expected: 0)
+
+ld1q {za0h.q[w12]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be 0.
+// CHECK-NEXT: ld1q {za0h.q[w12]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1q {za0h.q[w12, 1]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be 0.
+// CHECK-NEXT: ld1q {za0h.q[w12, 1]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate (expected: p0-p7)
-ld1q {za0h.q[w12]}, p8/z, [x0]
+ld1q {za0h.q[w12, 0]}, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
-// CHECK-NEXT: ld1q {za0h.q[w12]}, p8/z, [x0]
+// CHECK-NEXT: ld1q {za0h.q[w12, 0]}, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate qualifier (expected: /z)
-ld1q {za0h.q[w12]}, p0/m, [x0]
+ld1q {za0h.q[w12, 0]}, p0/m, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: ld1q {za0h.q[w12]}, p0/m, [x0]
+// CHECK-NEXT: ld1q {za0h.q[w12, 0]}, p0/m, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid memory operands
-ld1q {za0h.q[w12]}, p0/z, [w0]
+ld1q {za0h.q[w12, 0]}, p0/z, [w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: ld1q {za0h.q[w12]}, p0/z, [w0]
+// CHECK-NEXT: ld1q {za0h.q[w12, 0]}, p0/z, [w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1q {za0h.q[w12]}, p0/z, [x0, w0]
+ld1q {za0h.q[w12, 0]}, p0/z, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #4'
-// CHECK-NEXT: ld1q {za0h.q[w12]}, p0/z, [x0, w0]
+// CHECK-NEXT: ld1q {za0h.q[w12, 0]}, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1q {za0h.q[w12]}, p0/z, [x0, x0, lsl #5]
+ld1q {za0h.q[w12, 0]}, p0/z, [x0, x0, lsl #5]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #4'
-// CHECK-NEXT: ld1q {za0h.q[w12]}, p0/z, [x0, x0, lsl #5]
+// CHECK-NEXT: ld1q {za0h.q[w12, 0]}, p0/z, [x0, x0, lsl #5]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/ld1q.s b/llvm/test/MC/AArch64/SME/ld1q.s
index 9d6be44a5b545..4d679e338b7a0 100644
--- a/llvm/test/MC/AArch64/SME/ld1q.s
+++ b/llvm/test/MC/AArch64/SME/ld1q.s
@@ -15,146 +15,146 @@
// --------------------------------------------------------------------------//
// Horizontal
-ld1q {za0h.q[w12]}, p0/z, [x0, x0, lsl #4]
-// CHECK-INST: ld1q {za0h.q[w12]}, p0/z, [x0, x0, lsl #4]
+ld1q {za0h.q[w12, 0]}, p0/z, [x0, x0, lsl #4]
+// CHECK-INST: ld1q {za0h.q[w12, 0]}, p0/z, [x0, x0, lsl #4]
// CHECK-ENCODING: [0x00,0x00,0xc0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 c0 e1 <unknown>
-ld1q {za5h.q[w14]}, p5/z, [x10, x21, lsl #4]
-// CHECK-INST: ld1q {za5h.q[w14]}, p5/z, [x10, x21, lsl #4]
+ld1q {za5h.q[w14, 0]}, p5/z, [x10, x21, lsl #4]
+// CHECK-INST: ld1q {za5h.q[w14, 0]}, p5/z, [x10, x21, lsl #4]
// CHECK-ENCODING: [0x45,0x55,0xd5,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 d5 e1 <unknown>
-ld1q {za7h.q[w15]}, p3/z, [x13, x8, lsl #4]
-// CHECK-INST: ld1q {za7h.q[w15]}, p3/z, [x13, x8, lsl #4]
+ld1q {za7h.q[w15, 0]}, p3/z, [x13, x8, lsl #4]
+// CHECK-INST: ld1q {za7h.q[w15, 0]}, p3/z, [x13, x8, lsl #4]
// CHECK-ENCODING: [0xa7,0x6d,0xc8,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d c8 e1 <unknown>
-ld1q {za15h.q[w15]}, p7/z, [sp]
-// CHECK-INST: ld1q {za15h.q[w15]}, p7/z, [sp]
+ld1q {za15h.q[w15, 0]}, p7/z, [sp]
+// CHECK-INST: ld1q {za15h.q[w15, 0]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0x7f,0xdf,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f df e1 <unknown>
-ld1q {za5h.q[w12]}, p3/z, [x17, x16, lsl #4]
-// CHECK-INST: ld1q {za5h.q[w12]}, p3/z, [x17, x16, lsl #4]
+ld1q {za5h.q[w12, 0]}, p3/z, [x17, x16, lsl #4]
+// CHECK-INST: ld1q {za5h.q[w12, 0]}, p3/z, [x17, x16, lsl #4]
// CHECK-ENCODING: [0x25,0x0e,0xd0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e d0 e1 <unknown>
-ld1q {za1h.q[w12]}, p1/z, [x1, x30, lsl #4]
-// CHECK-INST: ld1q {za1h.q[w12]}, p1/z, [x1, x30, lsl #4]
+ld1q {za1h.q[w12, 0]}, p1/z, [x1, x30, lsl #4]
+// CHECK-INST: ld1q {za1h.q[w12, 0]}, p1/z, [x1, x30, lsl #4]
// CHECK-ENCODING: [0x21,0x04,0xde,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 de e1 <unknown>
-ld1q {za8h.q[w14]}, p5/z, [x19, x20, lsl #4]
-// CHECK-INST: ld1q {za8h.q[w14]}, p5/z, [x19, x20, lsl #4]
+ld1q {za8h.q[w14, 0]}, p5/z, [x19, x20, lsl #4]
+// CHECK-INST: ld1q {za8h.q[w14, 0]}, p5/z, [x19, x20, lsl #4]
// CHECK-ENCODING: [0x68,0x56,0xd4,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 d4 e1 <unknown>
-ld1q {za0h.q[w12]}, p6/z, [x12, x2, lsl #4]
-// CHECK-INST: ld1q {za0h.q[w12]}, p6/z, [x12, x2, lsl #4]
+ld1q {za0h.q[w12, 0]}, p6/z, [x12, x2, lsl #4]
+// CHECK-INST: ld1q {za0h.q[w12, 0]}, p6/z, [x12, x2, lsl #4]
// CHECK-ENCODING: [0x80,0x19,0xc2,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 c2 e1 <unknown>
-ld1q {za1h.q[w14]}, p2/z, [x1, x26, lsl #4]
-// CHECK-INST: ld1q {za1h.q[w14]}, p2/z, [x1, x26, lsl #4]
+ld1q {za1h.q[w14, 0]}, p2/z, [x1, x26, lsl #4]
+// CHECK-INST: ld1q {za1h.q[w14, 0]}, p2/z, [x1, x26, lsl #4]
// CHECK-ENCODING: [0x21,0x48,0xda,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 da e1 <unknown>
-ld1q {za13h.q[w12]}, p2/z, [x22, x30, lsl #4]
-// CHECK-INST: ld1q {za13h.q[w12]}, p2/z, [x22, x30, lsl #4]
+ld1q {za13h.q[w12, 0]}, p2/z, [x22, x30, lsl #4]
+// CHECK-INST: ld1q {za13h.q[w12, 0]}, p2/z, [x22, x30, lsl #4]
// CHECK-ENCODING: [0xcd,0x0a,0xde,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a de e1 <unknown>
-ld1q {za2h.q[w15]}, p5/z, [x9, x1, lsl #4]
-// CHECK-INST: ld1q {za2h.q[w15]}, p5/z, [x9, x1, lsl #4]
+ld1q {za2h.q[w15, 0]}, p5/z, [x9, x1, lsl #4]
+// CHECK-INST: ld1q {za2h.q[w15, 0]}, p5/z, [x9, x1, lsl #4]
// CHECK-ENCODING: [0x22,0x75,0xc1,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 c1 e1 <unknown>
-ld1q {za7h.q[w13]}, p2/z, [x12, x11, lsl #4]
-// CHECK-INST: ld1q {za7h.q[w13]}, p2/z, [x12, x11, lsl #4]
+ld1q {za7h.q[w13, 0]}, p2/z, [x12, x11, lsl #4]
+// CHECK-INST: ld1q {za7h.q[w13, 0]}, p2/z, [x12, x11, lsl #4]
// CHECK-ENCODING: [0x87,0x29,0xcb,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 cb e1 <unknown>
-ld1q za0h.q[w12], p0/z, [x0, x0, lsl #4]
-// CHECK-INST: ld1q {za0h.q[w12]}, p0/z, [x0, x0, lsl #4]
+ld1q za0h.q[w12, 0], p0/z, [x0, x0, lsl #4]
+// CHECK-INST: ld1q {za0h.q[w12, 0]}, p0/z, [x0, x0, lsl #4]
// CHECK-ENCODING: [0x00,0x00,0xc0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 c0 e1 <unknown>
-ld1q za5h.q[w14], p5/z, [x10, x21, lsl #4]
-// CHECK-INST: ld1q {za5h.q[w14]}, p5/z, [x10, x21, lsl #4]
+ld1q za5h.q[w14, 0], p5/z, [x10, x21, lsl #4]
+// CHECK-INST: ld1q {za5h.q[w14, 0]}, p5/z, [x10, x21, lsl #4]
// CHECK-ENCODING: [0x45,0x55,0xd5,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 d5 e1 <unknown>
-ld1q za7h.q[w15], p3/z, [x13, x8, lsl #4]
-// CHECK-INST: ld1q {za7h.q[w15]}, p3/z, [x13, x8, lsl #4]
+ld1q za7h.q[w15, 0], p3/z, [x13, x8, lsl #4]
+// CHECK-INST: ld1q {za7h.q[w15, 0]}, p3/z, [x13, x8, lsl #4]
// CHECK-ENCODING: [0xa7,0x6d,0xc8,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d c8 e1 <unknown>
-ld1q za15h.q[w15], p7/z, [sp]
-// CHECK-INST: ld1q {za15h.q[w15]}, p7/z, [sp]
+ld1q za15h.q[w15, 0], p7/z, [sp]
+// CHECK-INST: ld1q {za15h.q[w15, 0]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0x7f,0xdf,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f df e1 <unknown>
-ld1q za5h.q[w12], p3/z, [x17, x16, lsl #4]
-// CHECK-INST: ld1q {za5h.q[w12]}, p3/z, [x17, x16, lsl #4]
+ld1q za5h.q[w12, 0], p3/z, [x17, x16, lsl #4]
+// CHECK-INST: ld1q {za5h.q[w12, 0]}, p3/z, [x17, x16, lsl #4]
// CHECK-ENCODING: [0x25,0x0e,0xd0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e d0 e1 <unknown>
-ld1q za1h.q[w12], p1/z, [x1, x30, lsl #4]
-// CHECK-INST: ld1q {za1h.q[w12]}, p1/z, [x1, x30, lsl #4]
+ld1q za1h.q[w12, 0], p1/z, [x1, x30, lsl #4]
+// CHECK-INST: ld1q {za1h.q[w12, 0]}, p1/z, [x1, x30, lsl #4]
// CHECK-ENCODING: [0x21,0x04,0xde,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 de e1 <unknown>
-ld1q za8h.q[w14], p5/z, [x19, x20, lsl #4]
-// CHECK-INST: ld1q {za8h.q[w14]}, p5/z, [x19, x20, lsl #4]
+ld1q za8h.q[w14, 0], p5/z, [x19, x20, lsl #4]
+// CHECK-INST: ld1q {za8h.q[w14, 0]}, p5/z, [x19, x20, lsl #4]
// CHECK-ENCODING: [0x68,0x56,0xd4,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 d4 e1 <unknown>
-ld1q za0h.q[w12], p6/z, [x12, x2, lsl #4]
-// CHECK-INST: ld1q {za0h.q[w12]}, p6/z, [x12, x2, lsl #4]
+ld1q za0h.q[w12, 0], p6/z, [x12, x2, lsl #4]
+// CHECK-INST: ld1q {za0h.q[w12, 0]}, p6/z, [x12, x2, lsl #4]
// CHECK-ENCODING: [0x80,0x19,0xc2,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 c2 e1 <unknown>
-ld1q za1h.q[w14], p2/z, [x1, x26, lsl #4]
-// CHECK-INST: ld1q {za1h.q[w14]}, p2/z, [x1, x26, lsl #4]
+ld1q za1h.q[w14, 0], p2/z, [x1, x26, lsl #4]
+// CHECK-INST: ld1q {za1h.q[w14, 0]}, p2/z, [x1, x26, lsl #4]
// CHECK-ENCODING: [0x21,0x48,0xda,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 da e1 <unknown>
-ld1q za13h.q[w12], p2/z, [x22, x30, lsl #4]
-// CHECK-INST: ld1q {za13h.q[w12]}, p2/z, [x22, x30, lsl #4]
+ld1q za13h.q[w12, 0], p2/z, [x22, x30, lsl #4]
+// CHECK-INST: ld1q {za13h.q[w12, 0]}, p2/z, [x22, x30, lsl #4]
// CHECK-ENCODING: [0xcd,0x0a,0xde,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a de e1 <unknown>
-ld1q za2h.q[w15], p5/z, [x9, x1, lsl #4]
-// CHECK-INST: ld1q {za2h.q[w15]}, p5/z, [x9, x1, lsl #4]
+ld1q za2h.q[w15, 0], p5/z, [x9, x1, lsl #4]
+// CHECK-INST: ld1q {za2h.q[w15, 0]}, p5/z, [x9, x1, lsl #4]
// CHECK-ENCODING: [0x22,0x75,0xc1,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 c1 e1 <unknown>
-ld1q za7h.q[w13], p2/z, [x12, x11, lsl #4]
-// CHECK-INST: ld1q {za7h.q[w13]}, p2/z, [x12, x11, lsl #4]
+ld1q za7h.q[w13, 0], p2/z, [x12, x11, lsl #4]
+// CHECK-INST: ld1q {za7h.q[w13, 0]}, p2/z, [x12, x11, lsl #4]
// CHECK-ENCODING: [0x87,0x29,0xcb,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 cb e1 <unknown>
@@ -162,146 +162,146 @@ ld1q za7h.q[w13], p2/z, [x12, x11, lsl #4]
// --------------------------------------------------------------------------//
// Vertical
-ld1q {za0v.q[w12]}, p0/z, [x0, x0, lsl #4]
-// CHECK-INST: ld1q {za0v.q[w12]}, p0/z, [x0, x0, lsl #4]
+ld1q {za0v.q[w12, 0]}, p0/z, [x0, x0, lsl #4]
+// CHECK-INST: ld1q {za0v.q[w12, 0]}, p0/z, [x0, x0, lsl #4]
// CHECK-ENCODING: [0x00,0x80,0xc0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 c0 e1 <unknown>
-ld1q {za5v.q[w14]}, p5/z, [x10, x21, lsl #4]
-// CHECK-INST: ld1q {za5v.q[w14]}, p5/z, [x10, x21, lsl #4]
+ld1q {za5v.q[w14, 0]}, p5/z, [x10, x21, lsl #4]
+// CHECK-INST: ld1q {za5v.q[w14, 0]}, p5/z, [x10, x21, lsl #4]
// CHECK-ENCODING: [0x45,0xd5,0xd5,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 d5 e1 <unknown>
-ld1q {za7v.q[w15]}, p3/z, [x13, x8, lsl #4]
-// CHECK-INST: ld1q {za7v.q[w15]}, p3/z, [x13, x8, lsl #4]
+ld1q {za7v.q[w15, 0]}, p3/z, [x13, x8, lsl #4]
+// CHECK-INST: ld1q {za7v.q[w15, 0]}, p3/z, [x13, x8, lsl #4]
// CHECK-ENCODING: [0xa7,0xed,0xc8,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed c8 e1 <unknown>
-ld1q {za15v.q[w15]}, p7/z, [sp]
-// CHECK-INST: ld1q {za15v.q[w15]}, p7/z, [sp]
+ld1q {za15v.q[w15, 0]}, p7/z, [sp]
+// CHECK-INST: ld1q {za15v.q[w15, 0]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0xff,0xdf,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff df e1 <unknown>
-ld1q {za5v.q[w12]}, p3/z, [x17, x16, lsl #4]
-// CHECK-INST: ld1q {za5v.q[w12]}, p3/z, [x17, x16, lsl #4]
+ld1q {za5v.q[w12, 0]}, p3/z, [x17, x16, lsl #4]
+// CHECK-INST: ld1q {za5v.q[w12, 0]}, p3/z, [x17, x16, lsl #4]
// CHECK-ENCODING: [0x25,0x8e,0xd0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e d0 e1 <unknown>
-ld1q {za1v.q[w12]}, p1/z, [x1, x30, lsl #4]
-// CHECK-INST: ld1q {za1v.q[w12]}, p1/z, [x1, x30, lsl #4]
+ld1q {za1v.q[w12, 0]}, p1/z, [x1, x30, lsl #4]
+// CHECK-INST: ld1q {za1v.q[w12, 0]}, p1/z, [x1, x30, lsl #4]
// CHECK-ENCODING: [0x21,0x84,0xde,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 de e1 <unknown>
-ld1q {za8v.q[w14]}, p5/z, [x19, x20, lsl #4]
-// CHECK-INST: ld1q {za8v.q[w14]}, p5/z, [x19, x20, lsl #4]
+ld1q {za8v.q[w14, 0]}, p5/z, [x19, x20, lsl #4]
+// CHECK-INST: ld1q {za8v.q[w14, 0]}, p5/z, [x19, x20, lsl #4]
// CHECK-ENCODING: [0x68,0xd6,0xd4,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 d4 e1 <unknown>
-ld1q {za0v.q[w12]}, p6/z, [x12, x2, lsl #4]
-// CHECK-INST: ld1q {za0v.q[w12]}, p6/z, [x12, x2, lsl #4]
+ld1q {za0v.q[w12, 0]}, p6/z, [x12, x2, lsl #4]
+// CHECK-INST: ld1q {za0v.q[w12, 0]}, p6/z, [x12, x2, lsl #4]
// CHECK-ENCODING: [0x80,0x99,0xc2,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 c2 e1 <unknown>
-ld1q {za1v.q[w14]}, p2/z, [x1, x26, lsl #4]
-// CHECK-INST: ld1q {za1v.q[w14]}, p2/z, [x1, x26, lsl #4]
+ld1q {za1v.q[w14, 0]}, p2/z, [x1, x26, lsl #4]
+// CHECK-INST: ld1q {za1v.q[w14, 0]}, p2/z, [x1, x26, lsl #4]
// CHECK-ENCODING: [0x21,0xc8,0xda,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 da e1 <unknown>
-ld1q {za13v.q[w12]}, p2/z, [x22, x30, lsl #4]
-// CHECK-INST: ld1q {za13v.q[w12]}, p2/z, [x22, x30, lsl #4]
+ld1q {za13v.q[w12, 0]}, p2/z, [x22, x30, lsl #4]
+// CHECK-INST: ld1q {za13v.q[w12, 0]}, p2/z, [x22, x30, lsl #4]
// CHECK-ENCODING: [0xcd,0x8a,0xde,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a de e1 <unknown>
-ld1q {za2v.q[w15]}, p5/z, [x9, x1, lsl #4]
-// CHECK-INST: ld1q {za2v.q[w15]}, p5/z, [x9, x1, lsl #4]
+ld1q {za2v.q[w15, 0]}, p5/z, [x9, x1, lsl #4]
+// CHECK-INST: ld1q {za2v.q[w15, 0]}, p5/z, [x9, x1, lsl #4]
// CHECK-ENCODING: [0x22,0xf5,0xc1,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 c1 e1 <unknown>
-ld1q {za7v.q[w13]}, p2/z, [x12, x11, lsl #4]
-// CHECK-INST: ld1q {za7v.q[w13]}, p2/z, [x12, x11, lsl #4]
+ld1q {za7v.q[w13, 0]}, p2/z, [x12, x11, lsl #4]
+// CHECK-INST: ld1q {za7v.q[w13, 0]}, p2/z, [x12, x11, lsl #4]
// CHECK-ENCODING: [0x87,0xa9,0xcb,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 cb e1 <unknown>
-ld1q za0v.q[w12], p0/z, [x0, x0, lsl #4]
-// CHECK-INST: ld1q {za0v.q[w12]}, p0/z, [x0, x0, lsl #4]
+ld1q za0v.q[w12, 0], p0/z, [x0, x0, lsl #4]
+// CHECK-INST: ld1q {za0v.q[w12, 0]}, p0/z, [x0, x0, lsl #4]
// CHECK-ENCODING: [0x00,0x80,0xc0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 c0 e1 <unknown>
-ld1q za5v.q[w14], p5/z, [x10, x21, lsl #4]
-// CHECK-INST: ld1q {za5v.q[w14]}, p5/z, [x10, x21, lsl #4]
+ld1q za5v.q[w14, 0], p5/z, [x10, x21, lsl #4]
+// CHECK-INST: ld1q {za5v.q[w14, 0]}, p5/z, [x10, x21, lsl #4]
// CHECK-ENCODING: [0x45,0xd5,0xd5,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 d5 e1 <unknown>
-ld1q za7v.q[w15], p3/z, [x13, x8, lsl #4]
-// CHECK-INST: ld1q {za7v.q[w15]}, p3/z, [x13, x8, lsl #4]
+ld1q za7v.q[w15, 0], p3/z, [x13, x8, lsl #4]
+// CHECK-INST: ld1q {za7v.q[w15, 0]}, p3/z, [x13, x8, lsl #4]
// CHECK-ENCODING: [0xa7,0xed,0xc8,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed c8 e1 <unknown>
-ld1q za15v.q[w15], p7/z, [sp]
-// CHECK-INST: ld1q {za15v.q[w15]}, p7/z, [sp]
+ld1q za15v.q[w15, 0], p7/z, [sp]
+// CHECK-INST: ld1q {za15v.q[w15, 0]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0xff,0xdf,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff df e1 <unknown>
-ld1q za5v.q[w12], p3/z, [x17, x16, lsl #4]
-// CHECK-INST: ld1q {za5v.q[w12]}, p3/z, [x17, x16, lsl #4]
+ld1q za5v.q[w12, 0], p3/z, [x17, x16, lsl #4]
+// CHECK-INST: ld1q {za5v.q[w12, 0]}, p3/z, [x17, x16, lsl #4]
// CHECK-ENCODING: [0x25,0x8e,0xd0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e d0 e1 <unknown>
-ld1q za1v.q[w12], p1/z, [x1, x30, lsl #4]
-// CHECK-INST: ld1q {za1v.q[w12]}, p1/z, [x1, x30, lsl #4]
+ld1q za1v.q[w12, 0], p1/z, [x1, x30, lsl #4]
+// CHECK-INST: ld1q {za1v.q[w12, 0]}, p1/z, [x1, x30, lsl #4]
// CHECK-ENCODING: [0x21,0x84,0xde,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 de e1 <unknown>
-ld1q za8v.q[w14], p5/z, [x19, x20, lsl #4]
-// CHECK-INST: ld1q {za8v.q[w14]}, p5/z, [x19, x20, lsl #4]
+ld1q za8v.q[w14, 0], p5/z, [x19, x20, lsl #4]
+// CHECK-INST: ld1q {za8v.q[w14, 0]}, p5/z, [x19, x20, lsl #4]
// CHECK-ENCODING: [0x68,0xd6,0xd4,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 d4 e1 <unknown>
-ld1q za0v.q[w12], p6/z, [x12, x2, lsl #4]
-// CHECK-INST: ld1q {za0v.q[w12]}, p6/z, [x12, x2, lsl #4]
+ld1q za0v.q[w12, 0], p6/z, [x12, x2, lsl #4]
+// CHECK-INST: ld1q {za0v.q[w12, 0]}, p6/z, [x12, x2, lsl #4]
// CHECK-ENCODING: [0x80,0x99,0xc2,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 c2 e1 <unknown>
-ld1q za1v.q[w14], p2/z, [x1, x26, lsl #4]
-// CHECK-INST: ld1q {za1v.q[w14]}, p2/z, [x1, x26, lsl #4]
+ld1q za1v.q[w14, 0], p2/z, [x1, x26, lsl #4]
+// CHECK-INST: ld1q {za1v.q[w14, 0]}, p2/z, [x1, x26, lsl #4]
// CHECK-ENCODING: [0x21,0xc8,0xda,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 da e1 <unknown>
-ld1q za13v.q[w12], p2/z, [x22, x30, lsl #4]
-// CHECK-INST: ld1q {za13v.q[w12]}, p2/z, [x22, x30, lsl #4]
+ld1q za13v.q[w12, 0], p2/z, [x22, x30, lsl #4]
+// CHECK-INST: ld1q {za13v.q[w12, 0]}, p2/z, [x22, x30, lsl #4]
// CHECK-ENCODING: [0xcd,0x8a,0xde,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a de e1 <unknown>
-ld1q za2v.q[w15], p5/z, [x9, x1, lsl #4]
-// CHECK-INST: ld1q {za2v.q[w15]}, p5/z, [x9, x1, lsl #4]
+ld1q za2v.q[w15, 0], p5/z, [x9, x1, lsl #4]
+// CHECK-INST: ld1q {za2v.q[w15, 0]}, p5/z, [x9, x1, lsl #4]
// CHECK-ENCODING: [0x22,0xf5,0xc1,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 c1 e1 <unknown>
-ld1q za7v.q[w13], p2/z, [x12, x11, lsl #4]
-// CHECK-INST: ld1q {za7v.q[w13]}, p2/z, [x12, x11, lsl #4]
+ld1q za7v.q[w13, 0], p2/z, [x12, x11, lsl #4]
+// CHECK-INST: ld1q {za7v.q[w13, 0]}, p2/z, [x12, x11, lsl #4]
// CHECK-ENCODING: [0x87,0xa9,0xcb,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 cb e1 <unknown>
diff --git a/llvm/test/MC/AArch64/SME/ld1w-diagnostics.s b/llvm/test/MC/AArch64/SME/ld1w-diagnostics.s
index 4522871a13f7d..e382e94323900 100644
--- a/llvm/test/MC/AArch64/SME/ld1w-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/ld1w-diagnostics.s
@@ -3,32 +3,32 @@
// ------------------------------------------------------------------------- //
// Invalid tile (expected: za[0-3]h.s or za[0-3]v.s)
-ld1w {za4h.s[w12, #0]}, p0/z, [x0]
+ld1w {za4h.s[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: ld1w {za4h.s[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1w {za4h.s[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1w {za[w12, #0]}, p0/z, [x0]
+ld1w {za[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3]h.s or za[0-3]v.s
-// CHECK-NEXT: ld1w {za[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1w {za[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1w {za1v.h[w12, #0]}, p0/z, [x0]
+ld1w {za1v.h[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3]h.s or za[0-3]v.s
-// CHECK-NEXT: ld1w {za1v.h[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1w {za1v.h[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid vector select register (expected: w12-w15)
-ld1w {za0h.s[w11, #0]}, p0/z, [x0]
+ld1w {za0h.s[w11, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: ld1w {za0h.s[w11, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1w {za0h.s[w11, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1w {za0h.s[w16, #0]}, p0/z, [x0]
+ld1w {za0h.s[w16, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: ld1w {za0h.s[w16, #0]}, p0/z, [x0]
+// CHECK-NEXT: ld1w {za0h.s[w16, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
@@ -39,41 +39,41 @@ ld1w {za0h.s[w12]}, p0/z, [x0]
// CHECK-NEXT: ld1w {za0h.s[w12]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1w {za0h.s[w12, #4]}, p0/z, [x0]
+ld1w {za0h.s[w12, 4]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3].
-// CHECK-NEXT: ld1w {za0h.s[w12, #4]}, p0/z, [x0]
+// CHECK-NEXT: ld1w {za0h.s[w12, 4]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate (expected: p0-p7)
-ld1w {za0h.s[w12, #0]}, p8/z, [x0]
+ld1w {za0h.s[w12, 0]}, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
-// CHECK-NEXT: ld1w {za0h.s[w12, #0]}, p8/z, [x0]
+// CHECK-NEXT: ld1w {za0h.s[w12, 0]}, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate qualifier (expected: /z)
-ld1w {za0h.s[w12, #0]}, p0/m, [x0]
+ld1w {za0h.s[w12, 0]}, p0/m, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: ld1w {za0h.s[w12, #0]}, p0/m, [x0]
+// CHECK-NEXT: ld1w {za0h.s[w12, 0]}, p0/m, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid memory operands
-ld1w {za0h.s[w12, #0]}, p0/z, [w0]
+ld1w {za0h.s[w12, 0]}, p0/z, [w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: ld1w {za0h.s[w12, #0]}, p0/z, [w0]
+// CHECK-NEXT: ld1w {za0h.s[w12, 0]}, p0/z, [w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1w {za0h.s[w12, #0]}, p0/z, [x0, w0]
+ld1w {za0h.s[w12, 0]}, p0/z, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
-// CHECK-NEXT: ld1w {za0h.s[w12, #0]}, p0/z, [x0, w0]
+// CHECK-NEXT: ld1w {za0h.s[w12, 0]}, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-ld1w {za0h.s[w12, #0]}, p0/z, [x0, x0, lsl #3]
+ld1w {za0h.s[w12, 0]}, p0/z, [x0, x0, lsl #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
-// CHECK-NEXT: ld1w {za0h.s[w12, #0]}, p0/z, [x0, x0, lsl #3]
+// CHECK-NEXT: ld1w {za0h.s[w12, 0]}, p0/z, [x0, x0, lsl #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/ld1w.s b/llvm/test/MC/AArch64/SME/ld1w.s
index 0121bd520c7e0..b4fd19a2639a3 100644
--- a/llvm/test/MC/AArch64/SME/ld1w.s
+++ b/llvm/test/MC/AArch64/SME/ld1w.s
@@ -15,146 +15,146 @@
// --------------------------------------------------------------------------//
// Horizontal
-ld1w {za0h.s[w12, #0]}, p0/z, [x0, x0, lsl #2]
-// CHECK-INST: ld1w {za0h.s[w12, #0]}, p0/z, [x0, x0, lsl #2]
+ld1w {za0h.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
+// CHECK-INST: ld1w {za0h.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
// CHECK-ENCODING: [0x00,0x00,0x80,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 80 e0 <unknown>
-ld1w {za1h.s[w14, #1]}, p5/z, [x10, x21, lsl #2]
-// CHECK-INST: ld1w {za1h.s[w14, #1]}, p5/z, [x10, x21, lsl #2]
+ld1w {za1h.s[w14, 1]}, p5/z, [x10, x21, lsl #2]
+// CHECK-INST: ld1w {za1h.s[w14, 1]}, p5/z, [x10, x21, lsl #2]
// CHECK-ENCODING: [0x45,0x55,0x95,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 95 e0 <unknown>
-ld1w {za1h.s[w15, #3]}, p3/z, [x13, x8, lsl #2]
-// CHECK-INST: ld1w {za1h.s[w15, #3]}, p3/z, [x13, x8, lsl #2]
+ld1w {za1h.s[w15, 3]}, p3/z, [x13, x8, lsl #2]
+// CHECK-INST: ld1w {za1h.s[w15, 3]}, p3/z, [x13, x8, lsl #2]
// CHECK-ENCODING: [0xa7,0x6d,0x88,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 88 e0 <unknown>
-ld1w {za3h.s[w15, #3]}, p7/z, [sp]
-// CHECK-INST: ld1w {za3h.s[w15, #3]}, p7/z, [sp]
+ld1w {za3h.s[w15, 3]}, p7/z, [sp]
+// CHECK-INST: ld1w {za3h.s[w15, 3]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0x7f,0x9f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 9f e0 <unknown>
-ld1w {za1h.s[w12, #1]}, p3/z, [x17, x16, lsl #2]
-// CHECK-INST: ld1w {za1h.s[w12, #1]}, p3/z, [x17, x16, lsl #2]
+ld1w {za1h.s[w12, 1]}, p3/z, [x17, x16, lsl #2]
+// CHECK-INST: ld1w {za1h.s[w12, 1]}, p3/z, [x17, x16, lsl #2]
// CHECK-ENCODING: [0x25,0x0e,0x90,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 90 e0 <unknown>
-ld1w {za0h.s[w12, #1]}, p1/z, [x1, x30, lsl #2]
-// CHECK-INST: ld1w {za0h.s[w12, #1]}, p1/z, [x1, x30, lsl #2]
+ld1w {za0h.s[w12, 1]}, p1/z, [x1, x30, lsl #2]
+// CHECK-INST: ld1w {za0h.s[w12, 1]}, p1/z, [x1, x30, lsl #2]
// CHECK-ENCODING: [0x21,0x04,0x9e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 9e e0 <unknown>
-ld1w {za2h.s[w14, #0]}, p5/z, [x19, x20, lsl #2]
-// CHECK-INST: ld1w {za2h.s[w14, #0]}, p5/z, [x19, x20, lsl #2]
+ld1w {za2h.s[w14, 0]}, p5/z, [x19, x20, lsl #2]
+// CHECK-INST: ld1w {za2h.s[w14, 0]}, p5/z, [x19, x20, lsl #2]
// CHECK-ENCODING: [0x68,0x56,0x94,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 94 e0 <unknown>
-ld1w {za0h.s[w12, #0]}, p6/z, [x12, x2, lsl #2]
-// CHECK-INST: ld1w {za0h.s[w12, #0]}, p6/z, [x12, x2, lsl #2]
+ld1w {za0h.s[w12, 0]}, p6/z, [x12, x2, lsl #2]
+// CHECK-INST: ld1w {za0h.s[w12, 0]}, p6/z, [x12, x2, lsl #2]
// CHECK-ENCODING: [0x80,0x19,0x82,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 82 e0 <unknown>
-ld1w {za0h.s[w14, #1]}, p2/z, [x1, x26, lsl #2]
-// CHECK-INST: ld1w {za0h.s[w14, #1]}, p2/z, [x1, x26, lsl #2]
+ld1w {za0h.s[w14, 1]}, p2/z, [x1, x26, lsl #2]
+// CHECK-INST: ld1w {za0h.s[w14, 1]}, p2/z, [x1, x26, lsl #2]
// CHECK-ENCODING: [0x21,0x48,0x9a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 9a e0 <unknown>
-ld1w {za3h.s[w12, #1]}, p2/z, [x22, x30, lsl #2]
-// CHECK-INST: ld1w {za3h.s[w12, #1]}, p2/z, [x22, x30, lsl #2]
+ld1w {za3h.s[w12, 1]}, p2/z, [x22, x30, lsl #2]
+// CHECK-INST: ld1w {za3h.s[w12, 1]}, p2/z, [x22, x30, lsl #2]
// CHECK-ENCODING: [0xcd,0x0a,0x9e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 9e e0 <unknown>
-ld1w {za0h.s[w15, #2]}, p5/z, [x9, x1, lsl #2]
-// CHECK-INST: ld1w {za0h.s[w15, #2]}, p5/z, [x9, x1, lsl #2]
+ld1w {za0h.s[w15, 2]}, p5/z, [x9, x1, lsl #2]
+// CHECK-INST: ld1w {za0h.s[w15, 2]}, p5/z, [x9, x1, lsl #2]
// CHECK-ENCODING: [0x22,0x75,0x81,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 81 e0 <unknown>
-ld1w {za1h.s[w13, #3]}, p2/z, [x12, x11, lsl #2]
-// CHECK-INST: ld1w {za1h.s[w13, #3]}, p2/z, [x12, x11, lsl #2]
+ld1w {za1h.s[w13, 3]}, p2/z, [x12, x11, lsl #2]
+// CHECK-INST: ld1w {za1h.s[w13, 3]}, p2/z, [x12, x11, lsl #2]
// CHECK-ENCODING: [0x87,0x29,0x8b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 8b e0 <unknown>
-ld1w za0h.s[w12, #0], p0/z, [x0, x0, lsl #2]
-// CHECK-INST: ld1w {za0h.s[w12, #0]}, p0/z, [x0, x0, lsl #2]
+ld1w za0h.s[w12, 0], p0/z, [x0, x0, lsl #2]
+// CHECK-INST: ld1w {za0h.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
// CHECK-ENCODING: [0x00,0x00,0x80,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 80 e0 <unknown>
-ld1w za1h.s[w14, #1], p5/z, [x10, x21, lsl #2]
-// CHECK-INST: ld1w {za1h.s[w14, #1]}, p5/z, [x10, x21, lsl #2]
+ld1w za1h.s[w14, 1], p5/z, [x10, x21, lsl #2]
+// CHECK-INST: ld1w {za1h.s[w14, 1]}, p5/z, [x10, x21, lsl #2]
// CHECK-ENCODING: [0x45,0x55,0x95,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 95 e0 <unknown>
-ld1w za1h.s[w15, #3], p3/z, [x13, x8, lsl #2]
-// CHECK-INST: ld1w {za1h.s[w15, #3]}, p3/z, [x13, x8, lsl #2]
+ld1w za1h.s[w15, 3], p3/z, [x13, x8, lsl #2]
+// CHECK-INST: ld1w {za1h.s[w15, 3]}, p3/z, [x13, x8, lsl #2]
// CHECK-ENCODING: [0xa7,0x6d,0x88,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 88 e0 <unknown>
-ld1w za3h.s[w15, #3], p7/z, [sp]
-// CHECK-INST: ld1w {za3h.s[w15, #3]}, p7/z, [sp]
+ld1w za3h.s[w15, 3], p7/z, [sp]
+// CHECK-INST: ld1w {za3h.s[w15, 3]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0x7f,0x9f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 9f e0 <unknown>
-ld1w za1h.s[w12, #1], p3/z, [x17, x16, lsl #2]
-// CHECK-INST: ld1w {za1h.s[w12, #1]}, p3/z, [x17, x16, lsl #2]
+ld1w za1h.s[w12, 1], p3/z, [x17, x16, lsl #2]
+// CHECK-INST: ld1w {za1h.s[w12, 1]}, p3/z, [x17, x16, lsl #2]
// CHECK-ENCODING: [0x25,0x0e,0x90,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 90 e0 <unknown>
-ld1w za0h.s[w12, #1], p1/z, [x1, x30, lsl #2]
-// CHECK-INST: ld1w {za0h.s[w12, #1]}, p1/z, [x1, x30, lsl #2]
+ld1w za0h.s[w12, 1], p1/z, [x1, x30, lsl #2]
+// CHECK-INST: ld1w {za0h.s[w12, 1]}, p1/z, [x1, x30, lsl #2]
// CHECK-ENCODING: [0x21,0x04,0x9e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 9e e0 <unknown>
-ld1w za2h.s[w14, #0], p5/z, [x19, x20, lsl #2]
-// CHECK-INST: ld1w {za2h.s[w14, #0]}, p5/z, [x19, x20, lsl #2]
+ld1w za2h.s[w14, 0], p5/z, [x19, x20, lsl #2]
+// CHECK-INST: ld1w {za2h.s[w14, 0]}, p5/z, [x19, x20, lsl #2]
// CHECK-ENCODING: [0x68,0x56,0x94,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 94 e0 <unknown>
-ld1w za0h.s[w12, #0], p6/z, [x12, x2, lsl #2]
-// CHECK-INST: ld1w {za0h.s[w12, #0]}, p6/z, [x12, x2, lsl #2]
+ld1w za0h.s[w12, 0], p6/z, [x12, x2, lsl #2]
+// CHECK-INST: ld1w {za0h.s[w12, 0]}, p6/z, [x12, x2, lsl #2]
// CHECK-ENCODING: [0x80,0x19,0x82,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 82 e0 <unknown>
-ld1w za0h.s[w14, #1], p2/z, [x1, x26, lsl #2]
-// CHECK-INST: ld1w {za0h.s[w14, #1]}, p2/z, [x1, x26, lsl #2]
+ld1w za0h.s[w14, 1], p2/z, [x1, x26, lsl #2]
+// CHECK-INST: ld1w {za0h.s[w14, 1]}, p2/z, [x1, x26, lsl #2]
// CHECK-ENCODING: [0x21,0x48,0x9a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 9a e0 <unknown>
-ld1w za3h.s[w12, #1], p2/z, [x22, x30, lsl #2]
-// CHECK-INST: ld1w {za3h.s[w12, #1]}, p2/z, [x22, x30, lsl #2]
+ld1w za3h.s[w12, 1], p2/z, [x22, x30, lsl #2]
+// CHECK-INST: ld1w {za3h.s[w12, 1]}, p2/z, [x22, x30, lsl #2]
// CHECK-ENCODING: [0xcd,0x0a,0x9e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 9e e0 <unknown>
-ld1w za0h.s[w15, #2], p5/z, [x9, x1, lsl #2]
-// CHECK-INST: ld1w {za0h.s[w15, #2]}, p5/z, [x9, x1, lsl #2]
+ld1w za0h.s[w15, 2], p5/z, [x9, x1, lsl #2]
+// CHECK-INST: ld1w {za0h.s[w15, 2]}, p5/z, [x9, x1, lsl #2]
// CHECK-ENCODING: [0x22,0x75,0x81,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 81 e0 <unknown>
-ld1w za1h.s[w13, #3], p2/z, [x12, x11, lsl #2]
-// CHECK-INST: ld1w {za1h.s[w13, #3]}, p2/z, [x12, x11, lsl #2]
+ld1w za1h.s[w13, 3], p2/z, [x12, x11, lsl #2]
+// CHECK-INST: ld1w {za1h.s[w13, 3]}, p2/z, [x12, x11, lsl #2]
// CHECK-ENCODING: [0x87,0x29,0x8b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 8b e0 <unknown>
@@ -162,146 +162,146 @@ ld1w za1h.s[w13, #3], p2/z, [x12, x11, lsl #2]
// --------------------------------------------------------------------------//
// Vertical
-ld1w {za0v.s[w12, #0]}, p0/z, [x0, x0, lsl #2]
-// CHECK-INST: ld1w {za0v.s[w12, #0]}, p0/z, [x0, x0, lsl #2]
+ld1w {za0v.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
+// CHECK-INST: ld1w {za0v.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
// CHECK-ENCODING: [0x00,0x80,0x80,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 80 e0 <unknown>
-ld1w {za1v.s[w14, #1]}, p5/z, [x10, x21, lsl #2]
-// CHECK-INST: ld1w {za1v.s[w14, #1]}, p5/z, [x10, x21, lsl #2]
+ld1w {za1v.s[w14, 1]}, p5/z, [x10, x21, lsl #2]
+// CHECK-INST: ld1w {za1v.s[w14, 1]}, p5/z, [x10, x21, lsl #2]
// CHECK-ENCODING: [0x45,0xd5,0x95,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 95 e0 <unknown>
-ld1w {za1v.s[w15, #3]}, p3/z, [x13, x8, lsl #2]
-// CHECK-INST: ld1w {za1v.s[w15, #3]}, p3/z, [x13, x8, lsl #2]
+ld1w {za1v.s[w15, 3]}, p3/z, [x13, x8, lsl #2]
+// CHECK-INST: ld1w {za1v.s[w15, 3]}, p3/z, [x13, x8, lsl #2]
// CHECK-ENCODING: [0xa7,0xed,0x88,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 88 e0 <unknown>
-ld1w {za3v.s[w15, #3]}, p7/z, [sp]
-// CHECK-INST: ld1w {za3v.s[w15, #3]}, p7/z, [sp]
+ld1w {za3v.s[w15, 3]}, p7/z, [sp]
+// CHECK-INST: ld1w {za3v.s[w15, 3]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0xff,0x9f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 9f e0 <unknown>
-ld1w {za1v.s[w12, #1]}, p3/z, [x17, x16, lsl #2]
-// CHECK-INST: ld1w {za1v.s[w12, #1]}, p3/z, [x17, x16, lsl #2]
+ld1w {za1v.s[w12, 1]}, p3/z, [x17, x16, lsl #2]
+// CHECK-INST: ld1w {za1v.s[w12, 1]}, p3/z, [x17, x16, lsl #2]
// CHECK-ENCODING: [0x25,0x8e,0x90,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 90 e0 <unknown>
-ld1w {za0v.s[w12, #1]}, p1/z, [x1, x30, lsl #2]
-// CHECK-INST: ld1w {za0v.s[w12, #1]}, p1/z, [x1, x30, lsl #2]
+ld1w {za0v.s[w12, 1]}, p1/z, [x1, x30, lsl #2]
+// CHECK-INST: ld1w {za0v.s[w12, 1]}, p1/z, [x1, x30, lsl #2]
// CHECK-ENCODING: [0x21,0x84,0x9e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 9e e0 <unknown>
-ld1w {za2v.s[w14, #0]}, p5/z, [x19, x20, lsl #2]
-// CHECK-INST: ld1w {za2v.s[w14, #0]}, p5/z, [x19, x20, lsl #2]
+ld1w {za2v.s[w14, 0]}, p5/z, [x19, x20, lsl #2]
+// CHECK-INST: ld1w {za2v.s[w14, 0]}, p5/z, [x19, x20, lsl #2]
// CHECK-ENCODING: [0x68,0xd6,0x94,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 94 e0 <unknown>
-ld1w {za0v.s[w12, #0]}, p6/z, [x12, x2, lsl #2]
-// CHECK-INST: ld1w {za0v.s[w12, #0]}, p6/z, [x12, x2, lsl #2]
+ld1w {za0v.s[w12, 0]}, p6/z, [x12, x2, lsl #2]
+// CHECK-INST: ld1w {za0v.s[w12, 0]}, p6/z, [x12, x2, lsl #2]
// CHECK-ENCODING: [0x80,0x99,0x82,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 82 e0 <unknown>
-ld1w {za0v.s[w14, #1]}, p2/z, [x1, x26, lsl #2]
-// CHECK-INST: ld1w {za0v.s[w14, #1]}, p2/z, [x1, x26, lsl #2]
+ld1w {za0v.s[w14, 1]}, p2/z, [x1, x26, lsl #2]
+// CHECK-INST: ld1w {za0v.s[w14, 1]}, p2/z, [x1, x26, lsl #2]
// CHECK-ENCODING: [0x21,0xc8,0x9a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 9a e0 <unknown>
-ld1w {za3v.s[w12, #1]}, p2/z, [x22, x30, lsl #2]
-// CHECK-INST: ld1w {za3v.s[w12, #1]}, p2/z, [x22, x30, lsl #2]
+ld1w {za3v.s[w12, 1]}, p2/z, [x22, x30, lsl #2]
+// CHECK-INST: ld1w {za3v.s[w12, 1]}, p2/z, [x22, x30, lsl #2]
// CHECK-ENCODING: [0xcd,0x8a,0x9e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 9e e0 <unknown>
-ld1w {za0v.s[w15, #2]}, p5/z, [x9, x1, lsl #2]
-// CHECK-INST: ld1w {za0v.s[w15, #2]}, p5/z, [x9, x1, lsl #2]
+ld1w {za0v.s[w15, 2]}, p5/z, [x9, x1, lsl #2]
+// CHECK-INST: ld1w {za0v.s[w15, 2]}, p5/z, [x9, x1, lsl #2]
// CHECK-ENCODING: [0x22,0xf5,0x81,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 81 e0 <unknown>
-ld1w {za1v.s[w13, #3]}, p2/z, [x12, x11, lsl #2]
-// CHECK-INST: ld1w {za1v.s[w13, #3]}, p2/z, [x12, x11, lsl #2]
+ld1w {za1v.s[w13, 3]}, p2/z, [x12, x11, lsl #2]
+// CHECK-INST: ld1w {za1v.s[w13, 3]}, p2/z, [x12, x11, lsl #2]
// CHECK-ENCODING: [0x87,0xa9,0x8b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 8b e0 <unknown>
-ld1w za0v.s[w12, #0], p0/z, [x0, x0, lsl #2]
-// CHECK-INST: ld1w {za0v.s[w12, #0]}, p0/z, [x0, x0, lsl #2]
+ld1w za0v.s[w12, 0], p0/z, [x0, x0, lsl #2]
+// CHECK-INST: ld1w {za0v.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
// CHECK-ENCODING: [0x00,0x80,0x80,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 80 e0 <unknown>
-ld1w za1v.s[w14, #1], p5/z, [x10, x21, lsl #2]
-// CHECK-INST: ld1w {za1v.s[w14, #1]}, p5/z, [x10, x21, lsl #2]
+ld1w za1v.s[w14, 1], p5/z, [x10, x21, lsl #2]
+// CHECK-INST: ld1w {za1v.s[w14, 1]}, p5/z, [x10, x21, lsl #2]
// CHECK-ENCODING: [0x45,0xd5,0x95,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 95 e0 <unknown>
-ld1w za1v.s[w15, #3], p3/z, [x13, x8, lsl #2]
-// CHECK-INST: ld1w {za1v.s[w15, #3]}, p3/z, [x13, x8, lsl #2]
+ld1w za1v.s[w15, 3], p3/z, [x13, x8, lsl #2]
+// CHECK-INST: ld1w {za1v.s[w15, 3]}, p3/z, [x13, x8, lsl #2]
// CHECK-ENCODING: [0xa7,0xed,0x88,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 88 e0 <unknown>
-ld1w za3v.s[w15, #3], p7/z, [sp]
-// CHECK-INST: ld1w {za3v.s[w15, #3]}, p7/z, [sp]
+ld1w za3v.s[w15, 3], p7/z, [sp]
+// CHECK-INST: ld1w {za3v.s[w15, 3]}, p7/z, [sp]
// CHECK-ENCODING: [0xef,0xff,0x9f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 9f e0 <unknown>
-ld1w za1v.s[w12, #1], p3/z, [x17, x16, lsl #2]
-// CHECK-INST: ld1w {za1v.s[w12, #1]}, p3/z, [x17, x16, lsl #2]
+ld1w za1v.s[w12, 1], p3/z, [x17, x16, lsl #2]
+// CHECK-INST: ld1w {za1v.s[w12, 1]}, p3/z, [x17, x16, lsl #2]
// CHECK-ENCODING: [0x25,0x8e,0x90,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 90 e0 <unknown>
-ld1w za0v.s[w12, #1], p1/z, [x1, x30, lsl #2]
-// CHECK-INST: ld1w {za0v.s[w12, #1]}, p1/z, [x1, x30, lsl #2]
+ld1w za0v.s[w12, 1], p1/z, [x1, x30, lsl #2]
+// CHECK-INST: ld1w {za0v.s[w12, 1]}, p1/z, [x1, x30, lsl #2]
// CHECK-ENCODING: [0x21,0x84,0x9e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 9e e0 <unknown>
-ld1w za2v.s[w14, #0], p5/z, [x19, x20, lsl #2]
-// CHECK-INST: ld1w {za2v.s[w14, #0]}, p5/z, [x19, x20, lsl #2]
+ld1w za2v.s[w14, 0], p5/z, [x19, x20, lsl #2]
+// CHECK-INST: ld1w {za2v.s[w14, 0]}, p5/z, [x19, x20, lsl #2]
// CHECK-ENCODING: [0x68,0xd6,0x94,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 94 e0 <unknown>
-ld1w za0v.s[w12, #0], p6/z, [x12, x2, lsl #2]
-// CHECK-INST: ld1w {za0v.s[w12, #0]}, p6/z, [x12, x2, lsl #2]
+ld1w za0v.s[w12, 0], p6/z, [x12, x2, lsl #2]
+// CHECK-INST: ld1w {za0v.s[w12, 0]}, p6/z, [x12, x2, lsl #2]
// CHECK-ENCODING: [0x80,0x99,0x82,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 82 e0 <unknown>
-ld1w za0v.s[w14, #1], p2/z, [x1, x26, lsl #2]
-// CHECK-INST: ld1w {za0v.s[w14, #1]}, p2/z, [x1, x26, lsl #2]
+ld1w za0v.s[w14, 1], p2/z, [x1, x26, lsl #2]
+// CHECK-INST: ld1w {za0v.s[w14, 1]}, p2/z, [x1, x26, lsl #2]
// CHECK-ENCODING: [0x21,0xc8,0x9a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 9a e0 <unknown>
-ld1w za3v.s[w12, #1], p2/z, [x22, x30, lsl #2]
-// CHECK-INST: ld1w {za3v.s[w12, #1]}, p2/z, [x22, x30, lsl #2]
+ld1w za3v.s[w12, 1], p2/z, [x22, x30, lsl #2]
+// CHECK-INST: ld1w {za3v.s[w12, 1]}, p2/z, [x22, x30, lsl #2]
// CHECK-ENCODING: [0xcd,0x8a,0x9e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 9e e0 <unknown>
-ld1w za0v.s[w15, #2], p5/z, [x9, x1, lsl #2]
-// CHECK-INST: ld1w {za0v.s[w15, #2]}, p5/z, [x9, x1, lsl #2]
+ld1w za0v.s[w15, 2], p5/z, [x9, x1, lsl #2]
+// CHECK-INST: ld1w {za0v.s[w15, 2]}, p5/z, [x9, x1, lsl #2]
// CHECK-ENCODING: [0x22,0xf5,0x81,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 81 e0 <unknown>
-ld1w za1v.s[w13, #3], p2/z, [x12, x11, lsl #2]
-// CHECK-INST: ld1w {za1v.s[w13, #3]}, p2/z, [x12, x11, lsl #2]
+ld1w za1v.s[w13, 3], p2/z, [x12, x11, lsl #2]
+// CHECK-INST: ld1w {za1v.s[w13, 3]}, p2/z, [x12, x11, lsl #2]
// CHECK-ENCODING: [0x87,0xa9,0x8b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 8b e0 <unknown>
diff --git a/llvm/test/MC/AArch64/SME/ldr.s b/llvm/test/MC/AArch64/SME/ldr.s
index 6bfc1fe0290bd..f95dfe6314c9d 100644
--- a/llvm/test/MC/AArch64/SME/ldr.s
+++ b/llvm/test/MC/AArch64/SME/ldr.s
@@ -12,74 +12,74 @@
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-ldr za[w12, #0], [x0]
-// CHECK-INST: ldr za[w12, #0], [x0]
+ldr za[w12, 0], [x0]
+// CHECK-INST: ldr za[w12, 0], [x0]
// CHECK-ENCODING: [0x00,0x00,0x00,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 00 e1 <unknown>
-ldr za[w14, #5], [x10, #5, mul vl]
-// CHECK-INST: ldr za[w14, #5], [x10, #5, mul vl]
+ldr za[w14, 5], [x10, #5, mul vl]
+// CHECK-INST: ldr za[w14, 5], [x10, #5, mul vl]
// CHECK-ENCODING: [0x45,0x41,0x00,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 41 00 e1 <unknown>
-ldr za[w15, #7], [x13, #7, mul vl]
-// CHECK-INST: ldr za[w15, #7], [x13, #7, mul vl]
+ldr za[w15, 7], [x13, #7, mul vl]
+// CHECK-INST: ldr za[w15, 7], [x13, #7, mul vl]
// CHECK-ENCODING: [0xa7,0x61,0x00,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 61 00 e1 <unknown>
-ldr za[w15, #15], [sp, #15, mul vl]
-// CHECK-INST: ldr za[w15, #15], [sp, #15, mul vl]
+ldr za[w15, 15], [sp, #15, mul vl]
+// CHECK-INST: ldr za[w15, 15], [sp, #15, mul vl]
// CHECK-ENCODING: [0xef,0x63,0x00,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 63 00 e1 <unknown>
-ldr za[w12, #5], [x17, #5, mul vl]
-// CHECK-INST: ldr za[w12, #5], [x17, #5, mul vl]
+ldr za[w12, 5], [x17, #5, mul vl]
+// CHECK-INST: ldr za[w12, 5], [x17, #5, mul vl]
// CHECK-ENCODING: [0x25,0x02,0x00,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 02 00 e1 <unknown>
-ldr za[w12, #1], [x1, #1, mul vl]
-// CHECK-INST: ldr za[w12, #1], [x1, #1, mul vl]
+ldr za[w12, 1], [x1, #1, mul vl]
+// CHECK-INST: ldr za[w12, 1], [x1, #1, mul vl]
// CHECK-ENCODING: [0x21,0x00,0x00,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 00 00 e1 <unknown>
-ldr za[w14, #8], [x19, #8, mul vl]
-// CHECK-INST: ldr za[w14, #8], [x19, #8, mul vl]
+ldr za[w14, 8], [x19, #8, mul vl]
+// CHECK-INST: ldr za[w14, 8], [x19, #8, mul vl]
// CHECK-ENCODING: [0x68,0x42,0x00,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 42 00 e1 <unknown>
-ldr za[w12, #0], [x12]
-// CHECK-INST: ldr za[w12, #0], [x12]
+ldr za[w12, 0], [x12]
+// CHECK-INST: ldr za[w12, 0], [x12]
// CHECK-ENCODING: [0x80,0x01,0x00,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 01 00 e1 <unknown>
-ldr za[w14, #1], [x1, #1, mul vl]
-// CHECK-INST: ldr za[w14, #1], [x1, #1, mul vl]
+ldr za[w14, 1], [x1, #1, mul vl]
+// CHECK-INST: ldr za[w14, 1], [x1, #1, mul vl]
// CHECK-ENCODING: [0x21,0x40,0x00,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 40 00 e1 <unknown>
-ldr za[w12, #13], [x22, #13, mul vl]
-// CHECK-INST: ldr za[w12, #13], [x22, #13, mul vl]
+ldr za[w12, 13], [x22, #13, mul vl]
+// CHECK-INST: ldr za[w12, 13], [x22, #13, mul vl]
// CHECK-ENCODING: [0xcd,0x02,0x00,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 02 00 e1 <unknown>
-ldr za[w15, #2], [x9, #2, mul vl]
-// CHECK-INST: ldr za[w15, #2], [x9, #2, mul vl]
+ldr za[w15, 2], [x9, #2, mul vl]
+// CHECK-INST: ldr za[w15, 2], [x9, #2, mul vl]
// CHECK-ENCODING: [0x22,0x61,0x00,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 61 00 e1 <unknown>
-ldr za[w13, #7], [x12, #7, mul vl]
-// CHECK-INST: ldr za[w13, #7], [x12, #7, mul vl]
+ldr za[w13, 7], [x12, #7, mul vl]
+// CHECK-INST: ldr za[w13, 7], [x12, #7, mul vl]
// CHECK-ENCODING: [0x87,0x21,0x00,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 21 00 e1 <unknown>
diff --git a/llvm/test/MC/AArch64/SME/mova-diagnostics.s b/llvm/test/MC/AArch64/SME/mova-diagnostics.s
index f09ec110f698a..dfb7f98f3c978 100644
--- a/llvm/test/MC/AArch64/SME/mova-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/mova-diagnostics.s
@@ -3,9 +3,9 @@
// ------------------------------------------------------------------------- //
// Invalid predicate (expected: p0-p7)
-mova z0.b, p8/m, za0h.b[w12, #0]
+mova z0.b, p8/m, za0h.b[w12, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
-// CHECK-NEXT: mova z0.b, p8/m, za0h.b[w12, #0]
+// CHECK-NEXT: mova z0.b, p8/m, za0h.b[w12, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
@@ -13,56 +13,56 @@ mova z0.b, p8/m, za0h.b[w12, #0]
// tile-to-vector
-mova z0.b, p0/m, za1h.b[w12, #0]
+mova z0.b, p0/m, za1h.b[w12, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: mova z0.b, p0/m, za1h.b[w12, #0]
+// CHECK-NEXT: mova z0.b, p0/m, za1h.b[w12, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova z0.h, p0/m, za2h.h[w12, #0]
+mova z0.h, p0/m, za2h.h[w12, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: mova z0.h, p0/m, za2h.h[w12, #0]
+// CHECK-NEXT: mova z0.h, p0/m, za2h.h[w12, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova z0.s, p0/m, za4h.s[w12, #0]
+mova z0.s, p0/m, za4h.s[w12, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: mova z0.s, p0/m, za4h.s[w12, #0]
+// CHECK-NEXT: mova z0.s, p0/m, za4h.s[w12, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova z0.d, p0/m, za8h.d[w12, #0]
+mova z0.d, p0/m, za8h.d[w12, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: mova z0.d, p0/m, za8h.d[w12, #0]
+// CHECK-NEXT: mova z0.d, p0/m, za8h.d[w12, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova z0.q, p0/m, za16h.q[w12, #0]
+mova z0.q, p0/m, za16h.q[w12, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: mova z0.q, p0/m, za16h.q[w12, #0]
+// CHECK-NEXT: mova z0.q, p0/m, za16h.q[w12, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// vector-to-tile
-mova za1h.b[w12, #0], p0/m, z0.b
+mova za1h.b[w12, 0], p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: mova za1h.b[w12, #0], p0/m, z0.b
+// CHECK-NEXT: mova za1h.b[w12, 0], p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova za2h.h[w12, #0], p0/m, z0.h
+mova za2h.h[w12, 0], p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: mova za2h.h[w12, #0], p0/m, z0.h
+// CHECK-NEXT: mova za2h.h[w12, 0], p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova za4h.s[w12, #0], p0/m, z0.s
+mova za4h.s[w12, 0], p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: mova za4h.s[w12, #0], p0/m, z0.s
+// CHECK-NEXT: mova za4h.s[w12, 0], p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova za8h.d[w12, #0], p0/m, z0.d
+mova za8h.d[w12, 0], p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: mova za8h.d[w12, #0], p0/m, z0.d
+// CHECK-NEXT: mova za8h.d[w12, 0], p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova za16h.q[w12, #0], p0/m, z0.q
+mova za16h.q[w12, 0], p0/m, z0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: mova za16h.q[w12, #0], p0/m, z0.q
+// CHECK-NEXT: mova za16h.q[w12, 0], p0/m, z0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
@@ -70,60 +70,60 @@ mova za16h.q[w12, #0], p0/m, z0.q
// tile-to-vector
-mova z0.b, p0/m, za0h.h[w12, #0]
+mova z0.b, p0/m, za0h.h[w12, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za0h.b or za0v.b
-// CHECK-NEXT: mova z0.b, p0/m, za0h.h[w12, #0]
+// CHECK-NEXT: mova z0.b, p0/m, za0h.h[w12, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova z0.h, p0/m, za[w12, #0]
+mova z0.h, p0/m, za[w12, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-1]h.h or za[0-1]v.h
-// CHECK-NEXT: mova z0.h, p0/m, za[w12, #0]
+// CHECK-NEXT: mova z0.h, p0/m, za[w12, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova z0.s, p0/m, za2.s[w12, #0]
+mova z0.s, p0/m, za2.s[w12, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3]h.s or za[0-3]v.s
-// CHECK-NEXT: mova z0.s, p0/m, za2.s[w12, #0]
+// CHECK-NEXT: mova z0.s, p0/m, za2.s[w12, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova z0.d, p0/m, za2v.s[w12, #0]
+mova z0.d, p0/m, za2v.s[w12, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-7]h.d or za[0-7]v.d
-// CHECK-NEXT: mova z0.d, p0/m, za2v.s[w12, #0]
+// CHECK-NEXT: mova z0.d, p0/m, za2v.s[w12, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova z0.q, p0/m, za0h.b[w12, #0]
+mova z0.q, p0/m, za0h.b[w12, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-15]h.q or za[0-15]v.q
-// CHECK-NEXT: mova z0.q, p0/m, za0h.b[w12, #0]
+// CHECK-NEXT: mova z0.q, p0/m, za0h.b[w12, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// vector-to-tile, only one test here since the intended instruction variant is
// ambiguous when failing to match on the first operand.
-mova za[w12, #0], p0/m, z0.b
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-7]h.d or za[0-7]v.d
-// CHECK-NEXT: mova za[w12, #0], p0/m, z0.b
+mova za[w12, 0], p0/m, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-15]h.q or za[0-15]v.q
+// CHECK-NEXT: mova za[w12, 0], p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid vector select register (expected: w12-w15)
-mova z0.h, p0/m, za0h.h[w11, #0]
+mova z0.h, p0/m, za0h.h[w11, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: mova z0.h, p0/m, za0h.h[w11, #0]
+// CHECK-NEXT: mova z0.h, p0/m, za0h.h[w11, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova z0.s, p0/m, za0h.s[w16, #0]
+mova z0.s, p0/m, za0h.s[w16, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: mova z0.s, p0/m, za0h.s[w16, #0]
+// CHECK-NEXT: mova z0.s, p0/m, za0h.s[w16, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova za0h.d[w11, #0], p0/m, z0.d
+mova za0h.d[w11, 0], p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: mova za0h.d[w11, #0], p0/m, z0.d
+// CHECK-NEXT: mova za0h.d[w11, 0], p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova za0h.q[w16, #0], p0/m, z0.q
+mova za0h.q[w16, 0], p0/m, z0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: mova za0h.q[w16, #0], p0/m, z0.q
+// CHECK-NEXT: mova za0h.q[w16, 0], p0/m, z0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
@@ -133,132 +133,132 @@ mova za0h.q[w16, #0], p0/m, z0.q
// tile-to-vector
-mova z0.b, p0/m, za0h.b[w12, #16]
+mova z0.b, p0/m, za0h.b[w12, 16]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
-// CHECK-NEXT: mova z0.b, p0/m, za0h.b[w12, #16]
+// CHECK-NEXT: mova z0.b, p0/m, za0h.b[w12, 16]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova z0.h, p0/m, za0h.h[w12, #8]
+mova z0.h, p0/m, za0h.h[w12, 8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
-// CHECK-NEXT: mova z0.h, p0/m, za0h.h[w12, #8]
+// CHECK-NEXT: mova z0.h, p0/m, za0h.h[w12, 8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova z0.s, p0/m, za0h.s[w12, #4]
+mova z0.s, p0/m, za0h.s[w12, 4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3].
-// CHECK-NEXT: mova z0.s, p0/m, za0h.s[w12, #4]
+// CHECK-NEXT: mova z0.s, p0/m, za0h.s[w12, 4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova z0.d, p0/m, za0h.d[w12, #2]
+mova z0.d, p0/m, za0h.d[w12, 2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
-// CHECK-NEXT: mova z0.d, p0/m, za0h.d[w12, #2]
+// CHECK-NEXT: mova z0.d, p0/m, za0h.d[w12, 2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova z0.q, p0/m, za0h.q[w12, #0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: mova z0.q, p0/m, za0h.q[w12, #0]
+mova z0.q, p0/m, za0h.q[w12, 1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be 0.
+// CHECK-NEXT: mova z0.q, p0/m, za0h.q[w12, 1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mov z0.b, p0/m, za0h.b[w12, #16]
+mov z0.b, p0/m, za0h.b[w12, 16]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
-// CHECK-NEXT: mov z0.b, p0/m, za0h.b[w12, #16]
+// CHECK-NEXT: mov z0.b, p0/m, za0h.b[w12, 16]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mov z0.h, p0/m, za0h.h[w12, #8]
+mov z0.h, p0/m, za0h.h[w12, 8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
-// CHECK-NEXT: mov z0.h, p0/m, za0h.h[w12, #8]
+// CHECK-NEXT: mov z0.h, p0/m, za0h.h[w12, 8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mov z0.s, p0/m, za0h.s[w12, #4]
+mov z0.s, p0/m, za0h.s[w12, 4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3].
-// CHECK-NEXT: mov z0.s, p0/m, za0h.s[w12, #4]
+// CHECK-NEXT: mov z0.s, p0/m, za0h.s[w12, 4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mov z0.d, p0/m, za0h.d[w12, #2]
+mov z0.d, p0/m, za0h.d[w12, 2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
-// CHECK-NEXT: mov z0.d, p0/m, za0h.d[w12, #2]
+// CHECK-NEXT: mov z0.d, p0/m, za0h.d[w12, 2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mov z0.q, p0/m, za0h.q[w12, #0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: mov z0.q, p0/m, za0h.q[w12, #0]
+mov z0.q, p0/m, za0h.q[w12, 1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be 0.
+// CHECK-NEXT: mov z0.q, p0/m, za0h.q[w12, 1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// vector-to-tile
-mova za0h.b[w12, #16], p0/m, z0.b
+mova za0h.b[w12, 16], p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
-// CHECK-NEXT: mova za0h.b[w12, #16], p0/m, z0.b
+// CHECK-NEXT: mova za0h.b[w12, 16], p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova za0h.h[w12, #8], p0/m, z0.h
+mova za0h.h[w12, 8], p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
-// CHECK-NEXT: mova za0h.h[w12, #8], p0/m, z0.h
+// CHECK-NEXT: mova za0h.h[w12, 8], p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova za0h.s[w12, #4], p0/m, z0.s
+mova za0h.s[w12, 4], p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3].
-// CHECK-NEXT: mova za0h.s[w12, #4], p0/m, z0.s
+// CHECK-NEXT: mova za0h.s[w12, 4], p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova za0h.d[w12, #2], p0/m, z0.d
+mova za0h.d[w12, 2], p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
-// CHECK-NEXT: mova za0h.d[w12, #2], p0/m, z0.d
+// CHECK-NEXT: mova za0h.d[w12, 2], p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova za0h.q[w12, #0], p0/m, z0.q
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: mova za0h.q[w12, #0], p0/m, z0.q
+mova za0h.q[w12, 1], p0/m, z0.q
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be 0.
+// CHECK-NEXT: mova za0h.q[w12, 1], p0/m, z0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mov za0h.b[w12, #16], p0/m, z0.b
+mov za0h.b[w12, 16], p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
-// CHECK-NEXT: mov za0h.b[w12, #16], p0/m, z0.b
+// CHECK-NEXT: mov za0h.b[w12, 16], p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mov za0h.h[w12, #8], p0/m, z0.h
+mov za0h.h[w12, 8], p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
-// CHECK-NEXT: mov za0h.h[w12, #8], p0/m, z0.h
+// CHECK-NEXT: mov za0h.h[w12, 8], p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mov za0h.s[w12, #4], p0/m, z0.s
+mov za0h.s[w12, 4], p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3].
-// CHECK-NEXT: mov za0h.s[w12, #4], p0/m, z0.s
+// CHECK-NEXT: mov za0h.s[w12, 4], p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mov za0h.d[w12, #2], p0/m, z0.d
+mov za0h.d[w12, 2], p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
-// CHECK-NEXT: mov za0h.d[w12, #2], p0/m, z0.d
+// CHECK-NEXT: mov za0h.d[w12, 2], p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mov za0h.q[w12, #0], p0/m, z0.q
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: mov za0h.q[w12, #0], p0/m, z0.q
+mov za0h.q[w12, 1], p0/m, z0.q
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be 0.
+// CHECK-NEXT: mov za0h.q[w12, 1], p0/m, z0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid ZPR element width
-mova za0h.b[w12, #0], p0/m, z0.h
+mova za0h.b[w12, 0], p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
-// CHECK-NEXT: mova za0h.b[w12, #0], p0/m, z0.h
+// CHECK-NEXT: mova za0h.b[w12, 0], p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova za0h.h[w12, #0], p0/m, z0.s
+mova za0h.h[w12, 0], p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
-// CHECK-NEXT: mova za0h.h[w12, #0], p0/m, z0.s
+// CHECK-NEXT: mova za0h.h[w12, 0], p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova za0h.s[w12, #0], p0/m, z0.d
+mova za0h.s[w12, 0], p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
-// CHECK-NEXT: mova za0h.s[w12, #0], p0/m, z0.d
+// CHECK-NEXT: mova za0h.s[w12, 0], p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova za0h.d[w12, #0], p0/m, z0.q
+mova za0h.d[w12, 0], p0/m, z0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
-// CHECK-NEXT: mova za0h.d[w12, #0], p0/m, z0.q
+// CHECK-NEXT: mova za0h.d[w12, 0], p0/m, z0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-mova za0h.q[w12], p0/m, z0.b
+mova za0h.q[w12, 0], p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
-// CHECK-NEXT: mova za0h.q[w12], p0/m, z0.b
+// CHECK-NEXT: mova za0h.q[w12, 0], p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/mova.s b/llvm/test/MC/AArch64/SME/mova.s
index 4f736bfefc8a3..d5ef6c7d297e5 100644
--- a/llvm/test/MC/AArch64/SME/mova.s
+++ b/llvm/test/MC/AArch64/SME/mova.s
@@ -15,148 +15,148 @@
// --------------------------------------------------------------------------//
// Extract, tile to vector, horizontal, 8-bit
-mova z0.b, p0/m, za0h.b[w12, #0]
-// CHECK-INST: mov z0.b, p0/m, za0h.b[w12, #0]
+mova z0.b, p0/m, za0h.b[w12, 0]
+// CHECK-INST: mov z0.b, p0/m, za0h.b[w12, 0]
// CHECK-ENCODING: [0x00,0x00,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 02 c0 <unknown>
-mova z21.b, p5/m, za0h.b[w14, #10]
-// CHECK-INST: mov z21.b, p5/m, za0h.b[w14, #10]
+mova z21.b, p5/m, za0h.b[w14, 10]
+// CHECK-INST: mov z21.b, p5/m, za0h.b[w14, 10]
// CHECK-ENCODING: [0x55,0x55,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 55 02 c0 <unknown>
-mova z23.b, p3/m, za0h.b[w15, #13]
-// CHECK-INST: mov z23.b, p3/m, za0h.b[w15, #13]
+mova z23.b, p3/m, za0h.b[w15, 13]
+// CHECK-INST: mov z23.b, p3/m, za0h.b[w15, 13]
// CHECK-ENCODING: [0xb7,0x6d,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 6d 02 c0 <unknown>
-mova z31.b, p7/m, za0h.b[w15, #15]
-// CHECK-INST: mov z31.b, p7/m, za0h.b[w15, #15]
+mova z31.b, p7/m, za0h.b[w15, 15]
+// CHECK-INST: mov z31.b, p7/m, za0h.b[w15, 15]
// CHECK-ENCODING: [0xff,0x7d,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff 7d 02 c0 <unknown>
-mova z5.b, p3/m, za0h.b[w12, #1]
-// CHECK-INST: mov z5.b, p3/m, za0h.b[w12, #1]
+mova z5.b, p3/m, za0h.b[w12, 1]
+// CHECK-INST: mov z5.b, p3/m, za0h.b[w12, 1]
// CHECK-ENCODING: [0x25,0x0c,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0c 02 c0 <unknown>
-mova z1.b, p1/m, za0h.b[w12, #1]
-// CHECK-INST: mov z1.b, p1/m, za0h.b[w12, #1]
+mova z1.b, p1/m, za0h.b[w12, 1]
+// CHECK-INST: mov z1.b, p1/m, za0h.b[w12, 1]
// CHECK-ENCODING: [0x21,0x04,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 02 c0 <unknown>
-mova z24.b, p5/m, za0h.b[w14, #3]
-// CHECK-INST: mov z24.b, p5/m, za0h.b[w14, #3]
+mova z24.b, p5/m, za0h.b[w14, 3]
+// CHECK-INST: mov z24.b, p5/m, za0h.b[w14, 3]
// CHECK-ENCODING: [0x78,0x54,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 54 02 c0 <unknown>
-mova z0.b, p6/m, za0h.b[w12, #12]
-// CHECK-INST: mov z0.b, p6/m, za0h.b[w12, #12]
+mova z0.b, p6/m, za0h.b[w12, 12]
+// CHECK-INST: mov z0.b, p6/m, za0h.b[w12, 12]
// CHECK-ENCODING: [0x80,0x19,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 02 c0 <unknown>
-mova z17.b, p2/m, za0h.b[w14, #1]
-// CHECK-INST: mov z17.b, p2/m, za0h.b[w14, #1]
+mova z17.b, p2/m, za0h.b[w14, 1]
+// CHECK-INST: mov z17.b, p2/m, za0h.b[w14, 1]
// CHECK-ENCODING: [0x31,0x48,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 48 02 c0 <unknown>
-mova z29.b, p2/m, za0h.b[w12, #6]
-// CHECK-INST: mov z29.b, p2/m, za0h.b[w12, #6]
+mova z29.b, p2/m, za0h.b[w12, 6]
+// CHECK-INST: mov z29.b, p2/m, za0h.b[w12, 6]
// CHECK-ENCODING: [0xdd,0x08,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 08 02 c0 <unknown>
-mova z2.b, p5/m, za0h.b[w15, #9]
-// CHECK-INST: mov z2.b, p5/m, za0h.b[w15, #9]
+mova z2.b, p5/m, za0h.b[w15, 9]
+// CHECK-INST: mov z2.b, p5/m, za0h.b[w15, 9]
// CHECK-ENCODING: [0x22,0x75,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 02 c0 <unknown>
-mova z7.b, p2/m, za0h.b[w13, #12]
-// CHECK-INST: mov z7.b, p2/m, za0h.b[w13, #12]
+mova z7.b, p2/m, za0h.b[w13, 12]
+// CHECK-INST: mov z7.b, p2/m, za0h.b[w13, 12]
// CHECK-ENCODING: [0x87,0x29,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 02 c0 <unknown>
// Aliases
-mov z0.b, p0/m, za0h.b[w12, #0]
-// CHECK-INST: mov z0.b, p0/m, za0h.b[w12, #0]
+mov z0.b, p0/m, za0h.b[w12, 0]
+// CHECK-INST: mov z0.b, p0/m, za0h.b[w12, 0]
// CHECK-ENCODING: [0x00,0x00,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 02 c0 <unknown>
-mov z21.b, p5/m, za0h.b[w14, #10]
-// CHECK-INST: mov z21.b, p5/m, za0h.b[w14, #10]
+mov z21.b, p5/m, za0h.b[w14, 10]
+// CHECK-INST: mov z21.b, p5/m, za0h.b[w14, 10]
// CHECK-ENCODING: [0x55,0x55,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 55 02 c0 <unknown>
-mov z23.b, p3/m, za0h.b[w15, #13]
-// CHECK-INST: mov z23.b, p3/m, za0h.b[w15, #13]
+mov z23.b, p3/m, za0h.b[w15, 13]
+// CHECK-INST: mov z23.b, p3/m, za0h.b[w15, 13]
// CHECK-ENCODING: [0xb7,0x6d,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 6d 02 c0 <unknown>
-mov z31.b, p7/m, za0h.b[w15, #15]
-// CHECK-INST: mov z31.b, p7/m, za0h.b[w15, #15]
+mov z31.b, p7/m, za0h.b[w15, 15]
+// CHECK-INST: mov z31.b, p7/m, za0h.b[w15, 15]
// CHECK-ENCODING: [0xff,0x7d,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff 7d 02 c0 <unknown>
-mov z5.b, p3/m, za0h.b[w12, #1]
-// CHECK-INST: mov z5.b, p3/m, za0h.b[w12, #1]
+mov z5.b, p3/m, za0h.b[w12, 1]
+// CHECK-INST: mov z5.b, p3/m, za0h.b[w12, 1]
// CHECK-ENCODING: [0x25,0x0c,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0c 02 c0 <unknown>
-mov z1.b, p1/m, za0h.b[w12, #1]
-// CHECK-INST: mov z1.b, p1/m, za0h.b[w12, #1]
+mov z1.b, p1/m, za0h.b[w12, 1]
+// CHECK-INST: mov z1.b, p1/m, za0h.b[w12, 1]
// CHECK-ENCODING: [0x21,0x04,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 02 c0 <unknown>
-mov z24.b, p5/m, za0h.b[w14, #3]
-// CHECK-INST: mov z24.b, p5/m, za0h.b[w14, #3]
+mov z24.b, p5/m, za0h.b[w14, 3]
+// CHECK-INST: mov z24.b, p5/m, za0h.b[w14, 3]
// CHECK-ENCODING: [0x78,0x54,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 54 02 c0 <unknown>
-mov z0.b, p6/m, za0h.b[w12, #12]
-// CHECK-INST: mov z0.b, p6/m, za0h.b[w12, #12]
+mov z0.b, p6/m, za0h.b[w12, 12]
+// CHECK-INST: mov z0.b, p6/m, za0h.b[w12, 12]
// CHECK-ENCODING: [0x80,0x19,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 02 c0 <unknown>
-mov z17.b, p2/m, za0h.b[w14, #1]
-// CHECK-INST: mov z17.b, p2/m, za0h.b[w14, #1]
+mov z17.b, p2/m, za0h.b[w14, 1]
+// CHECK-INST: mov z17.b, p2/m, za0h.b[w14, 1]
// CHECK-ENCODING: [0x31,0x48,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 48 02 c0 <unknown>
-mov z29.b, p2/m, za0h.b[w12, #6]
-// CHECK-INST: mov z29.b, p2/m, za0h.b[w12, #6]
+mov z29.b, p2/m, za0h.b[w12, 6]
+// CHECK-INST: mov z29.b, p2/m, za0h.b[w12, 6]
// CHECK-ENCODING: [0xdd,0x08,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 08 02 c0 <unknown>
-mov z2.b, p5/m, za0h.b[w15, #9]
-// CHECK-INST: mov z2.b, p5/m, za0h.b[w15, #9]
+mov z2.b, p5/m, za0h.b[w15, 9]
+// CHECK-INST: mov z2.b, p5/m, za0h.b[w15, 9]
// CHECK-ENCODING: [0x22,0x75,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 02 c0 <unknown>
-mov z7.b, p2/m, za0h.b[w13, #12]
-// CHECK-INST: mov z7.b, p2/m, za0h.b[w13, #12]
+mov z7.b, p2/m, za0h.b[w13, 12]
+// CHECK-INST: mov z7.b, p2/m, za0h.b[w13, 12]
// CHECK-ENCODING: [0x87,0x29,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 02 c0 <unknown>
@@ -164,148 +164,148 @@ mov z7.b, p2/m, za0h.b[w13, #12]
// --------------------------------------------------------------------------//
// Extract, tile to vector, vertical, 8-bit
-mova z0.b, p0/m, za0v.b[w12, #0]
-// CHECK-INST: mov z0.b, p0/m, za0v.b[w12, #0]
+mova z0.b, p0/m, za0v.b[w12, 0]
+// CHECK-INST: mov z0.b, p0/m, za0v.b[w12, 0]
// CHECK-ENCODING: [0x00,0x80,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 02 c0 <unknown>
-mova z21.b, p5/m, za0v.b[w14, #10]
-// CHECK-INST: mov z21.b, p5/m, za0v.b[w14, #10]
+mova z21.b, p5/m, za0v.b[w14, 10]
+// CHECK-INST: mov z21.b, p5/m, za0v.b[w14, 10]
// CHECK-ENCODING: [0x55,0xd5,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 d5 02 c0 <unknown>
-mova z23.b, p3/m, za0v.b[w15, #13]
-// CHECK-INST: mov z23.b, p3/m, za0v.b[w15, #13]
+mova z23.b, p3/m, za0v.b[w15, 13]
+// CHECK-INST: mov z23.b, p3/m, za0v.b[w15, 13]
// CHECK-ENCODING: [0xb7,0xed,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 ed 02 c0 <unknown>
-mova z31.b, p7/m, za0v.b[w15, #15]
-// CHECK-INST: mov z31.b, p7/m, za0v.b[w15, #15]
+mova z31.b, p7/m, za0v.b[w15, 15]
+// CHECK-INST: mov z31.b, p7/m, za0v.b[w15, 15]
// CHECK-ENCODING: [0xff,0xfd,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff fd 02 c0 <unknown>
-mova z5.b, p3/m, za0v.b[w12, #1]
-// CHECK-INST: mov z5.b, p3/m, za0v.b[w12, #1]
+mova z5.b, p3/m, za0v.b[w12, 1]
+// CHECK-INST: mov z5.b, p3/m, za0v.b[w12, 1]
// CHECK-ENCODING: [0x25,0x8c,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8c 02 c0 <unknown>
-mova z1.b, p1/m, za0v.b[w12, #1]
-// CHECK-INST: mov z1.b, p1/m, za0v.b[w12, #1]
+mova z1.b, p1/m, za0v.b[w12, 1]
+// CHECK-INST: mov z1.b, p1/m, za0v.b[w12, 1]
// CHECK-ENCODING: [0x21,0x84,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 02 c0 <unknown>
-mova z24.b, p5/m, za0v.b[w14, #3]
-// CHECK-INST: mov z24.b, p5/m, za0v.b[w14, #3]
+mova z24.b, p5/m, za0v.b[w14, 3]
+// CHECK-INST: mov z24.b, p5/m, za0v.b[w14, 3]
// CHECK-ENCODING: [0x78,0xd4,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 d4 02 c0 <unknown>
-mova z0.b, p6/m, za0v.b[w12, #12]
-// CHECK-INST: mov z0.b, p6/m, za0v.b[w12, #12]
+mova z0.b, p6/m, za0v.b[w12, 12]
+// CHECK-INST: mov z0.b, p6/m, za0v.b[w12, 12]
// CHECK-ENCODING: [0x80,0x99,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 02 c0 <unknown>
-mova z17.b, p2/m, za0v.b[w14, #1]
-// CHECK-INST: mov z17.b, p2/m, za0v.b[w14, #1]
+mova z17.b, p2/m, za0v.b[w14, 1]
+// CHECK-INST: mov z17.b, p2/m, za0v.b[w14, 1]
// CHECK-ENCODING: [0x31,0xc8,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 c8 02 c0 <unknown>
-mova z29.b, p2/m, za0v.b[w12, #6]
-// CHECK-INST: mov z29.b, p2/m, za0v.b[w12, #6]
+mova z29.b, p2/m, za0v.b[w12, 6]
+// CHECK-INST: mov z29.b, p2/m, za0v.b[w12, 6]
// CHECK-ENCODING: [0xdd,0x88,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 88 02 c0 <unknown>
-mova z2.b, p5/m, za0v.b[w15, #9]
-// CHECK-INST: mov z2.b, p5/m, za0v.b[w15, #9]
+mova z2.b, p5/m, za0v.b[w15, 9]
+// CHECK-INST: mov z2.b, p5/m, za0v.b[w15, 9]
// CHECK-ENCODING: [0x22,0xf5,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 02 c0 <unknown>
-mova z7.b, p2/m, za0v.b[w13, #12]
-// CHECK-INST: mov z7.b, p2/m, za0v.b[w13, #12]
+mova z7.b, p2/m, za0v.b[w13, 12]
+// CHECK-INST: mov z7.b, p2/m, za0v.b[w13, 12]
// CHECK-ENCODING: [0x87,0xa9,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 02 c0 <unknown>
// Aliases
-mov z0.b, p0/m, za0v.b[w12, #0]
-// CHECK-INST: mov z0.b, p0/m, za0v.b[w12, #0]
+mov z0.b, p0/m, za0v.b[w12, 0]
+// CHECK-INST: mov z0.b, p0/m, za0v.b[w12, 0]
// CHECK-ENCODING: [0x00,0x80,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 02 c0 <unknown>
-mov z21.b, p5/m, za0v.b[w14, #10]
-// CHECK-INST: mov z21.b, p5/m, za0v.b[w14, #10]
+mov z21.b, p5/m, za0v.b[w14, 10]
+// CHECK-INST: mov z21.b, p5/m, za0v.b[w14, 10]
// CHECK-ENCODING: [0x55,0xd5,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 d5 02 c0 <unknown>
-mov z23.b, p3/m, za0v.b[w15, #13]
-// CHECK-INST: mov z23.b, p3/m, za0v.b[w15, #13]
+mov z23.b, p3/m, za0v.b[w15, 13]
+// CHECK-INST: mov z23.b, p3/m, za0v.b[w15, 13]
// CHECK-ENCODING: [0xb7,0xed,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 ed 02 c0 <unknown>
-mov z31.b, p7/m, za0v.b[w15, #15]
-// CHECK-INST: mov z31.b, p7/m, za0v.b[w15, #15]
+mov z31.b, p7/m, za0v.b[w15, 15]
+// CHECK-INST: mov z31.b, p7/m, za0v.b[w15, 15]
// CHECK-ENCODING: [0xff,0xfd,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff fd 02 c0 <unknown>
-mov z5.b, p3/m, za0v.b[w12, #1]
-// CHECK-INST: mov z5.b, p3/m, za0v.b[w12, #1]
+mov z5.b, p3/m, za0v.b[w12, 1]
+// CHECK-INST: mov z5.b, p3/m, za0v.b[w12, 1]
// CHECK-ENCODING: [0x25,0x8c,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8c 02 c0 <unknown>
-mov z1.b, p1/m, za0v.b[w12, #1]
-// CHECK-INST: mov z1.b, p1/m, za0v.b[w12, #1]
+mov z1.b, p1/m, za0v.b[w12, 1]
+// CHECK-INST: mov z1.b, p1/m, za0v.b[w12, 1]
// CHECK-ENCODING: [0x21,0x84,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 02 c0 <unknown>
-mov z24.b, p5/m, za0v.b[w14, #3]
-// CHECK-INST: mov z24.b, p5/m, za0v.b[w14, #3]
+mov z24.b, p5/m, za0v.b[w14, 3]
+// CHECK-INST: mov z24.b, p5/m, za0v.b[w14, 3]
// CHECK-ENCODING: [0x78,0xd4,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 d4 02 c0 <unknown>
-mov z0.b, p6/m, za0v.b[w12, #12]
-// CHECK-INST: mov z0.b, p6/m, za0v.b[w12, #12]
+mov z0.b, p6/m, za0v.b[w12, 12]
+// CHECK-INST: mov z0.b, p6/m, za0v.b[w12, 12]
// CHECK-ENCODING: [0x80,0x99,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 02 c0 <unknown>
-mov z17.b, p2/m, za0v.b[w14, #1]
-// CHECK-INST: mov z17.b, p2/m, za0v.b[w14, #1]
+mov z17.b, p2/m, za0v.b[w14, 1]
+// CHECK-INST: mov z17.b, p2/m, za0v.b[w14, 1]
// CHECK-ENCODING: [0x31,0xc8,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 c8 02 c0 <unknown>
-mov z29.b, p2/m, za0v.b[w12, #6]
-// CHECK-INST: mov z29.b, p2/m, za0v.b[w12, #6]
+mov z29.b, p2/m, za0v.b[w12, 6]
+// CHECK-INST: mov z29.b, p2/m, za0v.b[w12, 6]
// CHECK-ENCODING: [0xdd,0x88,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 88 02 c0 <unknown>
-mov z2.b, p5/m, za0v.b[w15, #9]
-// CHECK-INST: mov z2.b, p5/m, za0v.b[w15, #9]
+mov z2.b, p5/m, za0v.b[w15, 9]
+// CHECK-INST: mov z2.b, p5/m, za0v.b[w15, 9]
// CHECK-ENCODING: [0x22,0xf5,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 02 c0 <unknown>
-mov z7.b, p2/m, za0v.b[w13, #12]
-// CHECK-INST: mov z7.b, p2/m, za0v.b[w13, #12]
+mov z7.b, p2/m, za0v.b[w13, 12]
+// CHECK-INST: mov z7.b, p2/m, za0v.b[w13, 12]
// CHECK-ENCODING: [0x87,0xa9,0x02,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 02 c0 <unknown>
@@ -313,148 +313,148 @@ mov z7.b, p2/m, za0v.b[w13, #12]
// --------------------------------------------------------------------------//
// Extract, tile to vector, horizontal, 16-bit
-mova z0.h, p0/m, za0h.h[w12, #0]
-// CHECK-INST: mov z0.h, p0/m, za0h.h[w12, #0]
+mova z0.h, p0/m, za0h.h[w12, 0]
+// CHECK-INST: mov z0.h, p0/m, za0h.h[w12, 0]
// CHECK-ENCODING: [0x00,0x00,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 42 c0 <unknown>
-mova z21.h, p5/m, za1h.h[w14, #2]
-// CHECK-INST: mov z21.h, p5/m, za1h.h[w14, #2]
+mova z21.h, p5/m, za1h.h[w14, 2]
+// CHECK-INST: mov z21.h, p5/m, za1h.h[w14, 2]
// CHECK-ENCODING: [0x55,0x55,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 55 42 c0 <unknown>
-mova z23.h, p3/m, za1h.h[w15, #5]
-// CHECK-INST: mov z23.h, p3/m, za1h.h[w15, #5]
+mova z23.h, p3/m, za1h.h[w15, 5]
+// CHECK-INST: mov z23.h, p3/m, za1h.h[w15, 5]
// CHECK-ENCODING: [0xb7,0x6d,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 6d 42 c0 <unknown>
-mova z31.h, p7/m, za1h.h[w15, #7]
-// CHECK-INST: mov z31.h, p7/m, za1h.h[w15, #7]
+mova z31.h, p7/m, za1h.h[w15, 7]
+// CHECK-INST: mov z31.h, p7/m, za1h.h[w15, 7]
// CHECK-ENCODING: [0xff,0x7d,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff 7d 42 c0 <unknown>
-mova z5.h, p3/m, za0h.h[w12, #1]
-// CHECK-INST: mov z5.h, p3/m, za0h.h[w12, #1]
+mova z5.h, p3/m, za0h.h[w12, 1]
+// CHECK-INST: mov z5.h, p3/m, za0h.h[w12, 1]
// CHECK-ENCODING: [0x25,0x0c,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0c 42 c0 <unknown>
-mova z1.h, p1/m, za0h.h[w12, #1]
-// CHECK-INST: mov z1.h, p1/m, za0h.h[w12, #1]
+mova z1.h, p1/m, za0h.h[w12, 1]
+// CHECK-INST: mov z1.h, p1/m, za0h.h[w12, 1]
// CHECK-ENCODING: [0x21,0x04,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 42 c0 <unknown>
-mova z24.h, p5/m, za0h.h[w14, #3]
-// CHECK-INST: mov z24.h, p5/m, za0h.h[w14, #3]
+mova z24.h, p5/m, za0h.h[w14, 3]
+// CHECK-INST: mov z24.h, p5/m, za0h.h[w14, 3]
// CHECK-ENCODING: [0x78,0x54,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 54 42 c0 <unknown>
-mova z0.h, p6/m, za1h.h[w12, #4]
-// CHECK-INST: mov z0.h, p6/m, za1h.h[w12, #4]
+mova z0.h, p6/m, za1h.h[w12, 4]
+// CHECK-INST: mov z0.h, p6/m, za1h.h[w12, 4]
// CHECK-ENCODING: [0x80,0x19,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 42 c0 <unknown>
-mova z17.h, p2/m, za0h.h[w14, #1]
-// CHECK-INST: mov z17.h, p2/m, za0h.h[w14, #1]
+mova z17.h, p2/m, za0h.h[w14, 1]
+// CHECK-INST: mov z17.h, p2/m, za0h.h[w14, 1]
// CHECK-ENCODING: [0x31,0x48,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 48 42 c0 <unknown>
-mova z29.h, p2/m, za0h.h[w12, #6]
-// CHECK-INST: mov z29.h, p2/m, za0h.h[w12, #6]
+mova z29.h, p2/m, za0h.h[w12, 6]
+// CHECK-INST: mov z29.h, p2/m, za0h.h[w12, 6]
// CHECK-ENCODING: [0xdd,0x08,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 08 42 c0 <unknown>
-mova z2.h, p5/m, za1h.h[w15, #1]
-// CHECK-INST: mov z2.h, p5/m, za1h.h[w15, #1]
+mova z2.h, p5/m, za1h.h[w15, 1]
+// CHECK-INST: mov z2.h, p5/m, za1h.h[w15, 1]
// CHECK-ENCODING: [0x22,0x75,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 42 c0 <unknown>
-mova z7.h, p2/m, za1h.h[w13, #4]
-// CHECK-INST: mov z7.h, p2/m, za1h.h[w13, #4]
+mova z7.h, p2/m, za1h.h[w13, 4]
+// CHECK-INST: mov z7.h, p2/m, za1h.h[w13, 4]
// CHECK-ENCODING: [0x87,0x29,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 42 c0 <unknown>
// Aliases
-mov z0.h, p0/m, za0h.h[w12, #0]
-// CHECK-INST: mov z0.h, p0/m, za0h.h[w12, #0]
+mov z0.h, p0/m, za0h.h[w12, 0]
+// CHECK-INST: mov z0.h, p0/m, za0h.h[w12, 0]
// CHECK-ENCODING: [0x00,0x00,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 42 c0 <unknown>
-mov z21.h, p5/m, za1h.h[w14, #2]
-// CHECK-INST: mov z21.h, p5/m, za1h.h[w14, #2]
+mov z21.h, p5/m, za1h.h[w14, 2]
+// CHECK-INST: mov z21.h, p5/m, za1h.h[w14, 2]
// CHECK-ENCODING: [0x55,0x55,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 55 42 c0 <unknown>
-mov z23.h, p3/m, za1h.h[w15, #5]
-// CHECK-INST: mov z23.h, p3/m, za1h.h[w15, #5]
+mov z23.h, p3/m, za1h.h[w15, 5]
+// CHECK-INST: mov z23.h, p3/m, za1h.h[w15, 5]
// CHECK-ENCODING: [0xb7,0x6d,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 6d 42 c0 <unknown>
-mov z31.h, p7/m, za1h.h[w15, #7]
-// CHECK-INST: mov z31.h, p7/m, za1h.h[w15, #7]
+mov z31.h, p7/m, za1h.h[w15, 7]
+// CHECK-INST: mov z31.h, p7/m, za1h.h[w15, 7]
// CHECK-ENCODING: [0xff,0x7d,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff 7d 42 c0 <unknown>
-mov z5.h, p3/m, za0h.h[w12, #1]
-// CHECK-INST: mov z5.h, p3/m, za0h.h[w12, #1]
+mov z5.h, p3/m, za0h.h[w12, 1]
+// CHECK-INST: mov z5.h, p3/m, za0h.h[w12, 1]
// CHECK-ENCODING: [0x25,0x0c,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0c 42 c0 <unknown>
-mov z1.h, p1/m, za0h.h[w12, #1]
-// CHECK-INST: mov z1.h, p1/m, za0h.h[w12, #1]
+mov z1.h, p1/m, za0h.h[w12, 1]
+// CHECK-INST: mov z1.h, p1/m, za0h.h[w12, 1]
// CHECK-ENCODING: [0x21,0x04,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 42 c0 <unknown>
-mov z24.h, p5/m, za0h.h[w14, #3]
-// CHECK-INST: mov z24.h, p5/m, za0h.h[w14, #3]
+mov z24.h, p5/m, za0h.h[w14, 3]
+// CHECK-INST: mov z24.h, p5/m, za0h.h[w14, 3]
// CHECK-ENCODING: [0x78,0x54,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 54 42 c0 <unknown>
-mov z0.h, p6/m, za1h.h[w12, #4]
-// CHECK-INST: mov z0.h, p6/m, za1h.h[w12, #4]
+mov z0.h, p6/m, za1h.h[w12, 4]
+// CHECK-INST: mov z0.h, p6/m, za1h.h[w12, 4]
// CHECK-ENCODING: [0x80,0x19,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 42 c0 <unknown>
-mov z17.h, p2/m, za0h.h[w14, #1]
-// CHECK-INST: mov z17.h, p2/m, za0h.h[w14, #1]
+mov z17.h, p2/m, za0h.h[w14, 1]
+// CHECK-INST: mov z17.h, p2/m, za0h.h[w14, 1]
// CHECK-ENCODING: [0x31,0x48,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 48 42 c0 <unknown>
-mov z29.h, p2/m, za0h.h[w12, #6]
-// CHECK-INST: mov z29.h, p2/m, za0h.h[w12, #6]
+mov z29.h, p2/m, za0h.h[w12, 6]
+// CHECK-INST: mov z29.h, p2/m, za0h.h[w12, 6]
// CHECK-ENCODING: [0xdd,0x08,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 08 42 c0 <unknown>
-mov z2.h, p5/m, za1h.h[w15, #1]
-// CHECK-INST: mov z2.h, p5/m, za1h.h[w15, #1]
+mov z2.h, p5/m, za1h.h[w15, 1]
+// CHECK-INST: mov z2.h, p5/m, za1h.h[w15, 1]
// CHECK-ENCODING: [0x22,0x75,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 42 c0 <unknown>
-mov z7.h, p2/m, za1h.h[w13, #4]
-// CHECK-INST: mov z7.h, p2/m, za1h.h[w13, #4]
+mov z7.h, p2/m, za1h.h[w13, 4]
+// CHECK-INST: mov z7.h, p2/m, za1h.h[w13, 4]
// CHECK-ENCODING: [0x87,0x29,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 42 c0 <unknown>
@@ -462,148 +462,148 @@ mov z7.h, p2/m, za1h.h[w13, #4]
// --------------------------------------------------------------------------//
// Extract, tile to vector, vertical, 16-bit
-mova z0.h, p0/m, za0v.h[w12, #0]
-// CHECK-INST: mov z0.h, p0/m, za0v.h[w12, #0]
+mova z0.h, p0/m, za0v.h[w12, 0]
+// CHECK-INST: mov z0.h, p0/m, za0v.h[w12, 0]
// CHECK-ENCODING: [0x00,0x80,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 42 c0 <unknown>
-mova z21.h, p5/m, za1v.h[w14, #2]
-// CHECK-INST: mov z21.h, p5/m, za1v.h[w14, #2]
+mova z21.h, p5/m, za1v.h[w14, 2]
+// CHECK-INST: mov z21.h, p5/m, za1v.h[w14, 2]
// CHECK-ENCODING: [0x55,0xd5,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 d5 42 c0 <unknown>
-mova z23.h, p3/m, za1v.h[w15, #5]
-// CHECK-INST: mov z23.h, p3/m, za1v.h[w15, #5]
+mova z23.h, p3/m, za1v.h[w15, 5]
+// CHECK-INST: mov z23.h, p3/m, za1v.h[w15, 5]
// CHECK-ENCODING: [0xb7,0xed,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 ed 42 c0 <unknown>
-mova z31.h, p7/m, za1v.h[w15, #7]
-// CHECK-INST: mov z31.h, p7/m, za1v.h[w15, #7]
+mova z31.h, p7/m, za1v.h[w15, 7]
+// CHECK-INST: mov z31.h, p7/m, za1v.h[w15, 7]
// CHECK-ENCODING: [0xff,0xfd,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff fd 42 c0 <unknown>
-mova z5.h, p3/m, za0v.h[w12, #1]
-// CHECK-INST: mov z5.h, p3/m, za0v.h[w12, #1]
+mova z5.h, p3/m, za0v.h[w12, 1]
+// CHECK-INST: mov z5.h, p3/m, za0v.h[w12, 1]
// CHECK-ENCODING: [0x25,0x8c,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8c 42 c0 <unknown>
-mova z1.h, p1/m, za0v.h[w12, #1]
-// CHECK-INST: mov z1.h, p1/m, za0v.h[w12, #1]
+mova z1.h, p1/m, za0v.h[w12, 1]
+// CHECK-INST: mov z1.h, p1/m, za0v.h[w12, 1]
// CHECK-ENCODING: [0x21,0x84,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 42 c0 <unknown>
-mova z24.h, p5/m, za0v.h[w14, #3]
-// CHECK-INST: mov z24.h, p5/m, za0v.h[w14, #3]
+mova z24.h, p5/m, za0v.h[w14, 3]
+// CHECK-INST: mov z24.h, p5/m, za0v.h[w14, 3]
// CHECK-ENCODING: [0x78,0xd4,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 d4 42 c0 <unknown>
-mova z0.h, p6/m, za1v.h[w12, #4]
-// CHECK-INST: mov z0.h, p6/m, za1v.h[w12, #4]
+mova z0.h, p6/m, za1v.h[w12, 4]
+// CHECK-INST: mov z0.h, p6/m, za1v.h[w12, 4]
// CHECK-ENCODING: [0x80,0x99,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 42 c0 <unknown>
-mova z17.h, p2/m, za0v.h[w14, #1]
-// CHECK-INST: mov z17.h, p2/m, za0v.h[w14, #1]
+mova z17.h, p2/m, za0v.h[w14, 1]
+// CHECK-INST: mov z17.h, p2/m, za0v.h[w14, 1]
// CHECK-ENCODING: [0x31,0xc8,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 c8 42 c0 <unknown>
-mova z29.h, p2/m, za0v.h[w12, #6]
-// CHECK-INST: mov z29.h, p2/m, za0v.h[w12, #6]
+mova z29.h, p2/m, za0v.h[w12, 6]
+// CHECK-INST: mov z29.h, p2/m, za0v.h[w12, 6]
// CHECK-ENCODING: [0xdd,0x88,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 88 42 c0 <unknown>
-mova z2.h, p5/m, za1v.h[w15, #1]
-// CHECK-INST: mov z2.h, p5/m, za1v.h[w15, #1]
+mova z2.h, p5/m, za1v.h[w15, 1]
+// CHECK-INST: mov z2.h, p5/m, za1v.h[w15, 1]
// CHECK-ENCODING: [0x22,0xf5,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 42 c0 <unknown>
-mova z7.h, p2/m, za1v.h[w13, #4]
-// CHECK-INST: mov z7.h, p2/m, za1v.h[w13, #4]
+mova z7.h, p2/m, za1v.h[w13, 4]
+// CHECK-INST: mov z7.h, p2/m, za1v.h[w13, 4]
// CHECK-ENCODING: [0x87,0xa9,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 42 c0 <unknown>
// Aliases
-mov z0.h, p0/m, za0v.h[w12, #0]
-// CHECK-INST: mov z0.h, p0/m, za0v.h[w12, #0]
+mov z0.h, p0/m, za0v.h[w12, 0]
+// CHECK-INST: mov z0.h, p0/m, za0v.h[w12, 0]
// CHECK-ENCODING: [0x00,0x80,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 42 c0 <unknown>
-mov z21.h, p5/m, za1v.h[w14, #2]
-// CHECK-INST: mov z21.h, p5/m, za1v.h[w14, #2]
+mov z21.h, p5/m, za1v.h[w14, 2]
+// CHECK-INST: mov z21.h, p5/m, za1v.h[w14, 2]
// CHECK-ENCODING: [0x55,0xd5,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 d5 42 c0 <unknown>
-mov z23.h, p3/m, za1v.h[w15, #5]
-// CHECK-INST: mov z23.h, p3/m, za1v.h[w15, #5]
+mov z23.h, p3/m, za1v.h[w15, 5]
+// CHECK-INST: mov z23.h, p3/m, za1v.h[w15, 5]
// CHECK-ENCODING: [0xb7,0xed,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 ed 42 c0 <unknown>
-mov z31.h, p7/m, za1v.h[w15, #7]
-// CHECK-INST: mov z31.h, p7/m, za1v.h[w15, #7]
+mov z31.h, p7/m, za1v.h[w15, 7]
+// CHECK-INST: mov z31.h, p7/m, za1v.h[w15, 7]
// CHECK-ENCODING: [0xff,0xfd,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff fd 42 c0 <unknown>
-mov z5.h, p3/m, za0v.h[w12, #1]
-// CHECK-INST: mov z5.h, p3/m, za0v.h[w12, #1]
+mov z5.h, p3/m, za0v.h[w12, 1]
+// CHECK-INST: mov z5.h, p3/m, za0v.h[w12, 1]
// CHECK-ENCODING: [0x25,0x8c,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8c 42 c0 <unknown>
-mov z1.h, p1/m, za0v.h[w12, #1]
-// CHECK-INST: mov z1.h, p1/m, za0v.h[w12, #1]
+mov z1.h, p1/m, za0v.h[w12, 1]
+// CHECK-INST: mov z1.h, p1/m, za0v.h[w12, 1]
// CHECK-ENCODING: [0x21,0x84,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 42 c0 <unknown>
-mov z24.h, p5/m, za0v.h[w14, #3]
-// CHECK-INST: mov z24.h, p5/m, za0v.h[w14, #3]
+mov z24.h, p5/m, za0v.h[w14, 3]
+// CHECK-INST: mov z24.h, p5/m, za0v.h[w14, 3]
// CHECK-ENCODING: [0x78,0xd4,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 d4 42 c0 <unknown>
-mov z0.h, p6/m, za1v.h[w12, #4]
-// CHECK-INST: mov z0.h, p6/m, za1v.h[w12, #4]
+mov z0.h, p6/m, za1v.h[w12, 4]
+// CHECK-INST: mov z0.h, p6/m, za1v.h[w12, 4]
// CHECK-ENCODING: [0x80,0x99,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 42 c0 <unknown>
-mov z17.h, p2/m, za0v.h[w14, #1]
-// CHECK-INST: mov z17.h, p2/m, za0v.h[w14, #1]
+mov z17.h, p2/m, za0v.h[w14, 1]
+// CHECK-INST: mov z17.h, p2/m, za0v.h[w14, 1]
// CHECK-ENCODING: [0x31,0xc8,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 c8 42 c0 <unknown>
-mov z29.h, p2/m, za0v.h[w12, #6]
-// CHECK-INST: mov z29.h, p2/m, za0v.h[w12, #6]
+mov z29.h, p2/m, za0v.h[w12, 6]
+// CHECK-INST: mov z29.h, p2/m, za0v.h[w12, 6]
// CHECK-ENCODING: [0xdd,0x88,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 88 42 c0 <unknown>
-mov z2.h, p5/m, za1v.h[w15, #1]
-// CHECK-INST: mov z2.h, p5/m, za1v.h[w15, #1]
+mov z2.h, p5/m, za1v.h[w15, 1]
+// CHECK-INST: mov z2.h, p5/m, za1v.h[w15, 1]
// CHECK-ENCODING: [0x22,0xf5,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 42 c0 <unknown>
-mov z7.h, p2/m, za1v.h[w13, #4]
-// CHECK-INST: mov z7.h, p2/m, za1v.h[w13, #4]
+mov z7.h, p2/m, za1v.h[w13, 4]
+// CHECK-INST: mov z7.h, p2/m, za1v.h[w13, 4]
// CHECK-ENCODING: [0x87,0xa9,0x42,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 42 c0 <unknown>
@@ -611,148 +611,148 @@ mov z7.h, p2/m, za1v.h[w13, #4]
// --------------------------------------------------------------------------//
// Extract, tile to vector, horizontal, 32-bit
-mova z0.s, p0/m, za0h.s[w12, #0]
-// CHECK-INST: mov z0.s, p0/m, za0h.s[w12, #0]
+mova z0.s, p0/m, za0h.s[w12, 0]
+// CHECK-INST: mov z0.s, p0/m, za0h.s[w12, 0]
// CHECK-ENCODING: [0x00,0x00,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 82 c0 <unknown>
-mova z21.s, p5/m, za2h.s[w14, #2]
-// CHECK-INST: mov z21.s, p5/m, za2h.s[w14, #2]
+mova z21.s, p5/m, za2h.s[w14, 2]
+// CHECK-INST: mov z21.s, p5/m, za2h.s[w14, 2]
// CHECK-ENCODING: [0x55,0x55,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 55 82 c0 <unknown>
-mova z23.s, p3/m, za3h.s[w15, #1]
-// CHECK-INST: mov z23.s, p3/m, za3h.s[w15, #1]
+mova z23.s, p3/m, za3h.s[w15, 1]
+// CHECK-INST: mov z23.s, p3/m, za3h.s[w15, 1]
// CHECK-ENCODING: [0xb7,0x6d,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 6d 82 c0 <unknown>
-mova z31.s, p7/m, za3h.s[w15, #3]
-// CHECK-INST: mov z31.s, p7/m, za3h.s[w15, #3]
+mova z31.s, p7/m, za3h.s[w15, 3]
+// CHECK-INST: mov z31.s, p7/m, za3h.s[w15, 3]
// CHECK-ENCODING: [0xff,0x7d,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff 7d 82 c0 <unknown>
-mova z5.s, p3/m, za0h.s[w12, #1]
-// CHECK-INST: mov z5.s, p3/m, za0h.s[w12, #1]
+mova z5.s, p3/m, za0h.s[w12, 1]
+// CHECK-INST: mov z5.s, p3/m, za0h.s[w12, 1]
// CHECK-ENCODING: [0x25,0x0c,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0c 82 c0 <unknown>
-mova z1.s, p1/m, za0h.s[w12, #1]
-// CHECK-INST: mov z1.s, p1/m, za0h.s[w12, #1]
+mova z1.s, p1/m, za0h.s[w12, 1]
+// CHECK-INST: mov z1.s, p1/m, za0h.s[w12, 1]
// CHECK-ENCODING: [0x21,0x04,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 82 c0 <unknown>
-mova z24.s, p5/m, za0h.s[w14, #3]
-// CHECK-INST: mov z24.s, p5/m, za0h.s[w14, #3]
+mova z24.s, p5/m, za0h.s[w14, 3]
+// CHECK-INST: mov z24.s, p5/m, za0h.s[w14, 3]
// CHECK-ENCODING: [0x78,0x54,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 54 82 c0 <unknown>
-mova z0.s, p6/m, za3h.s[w12, #0]
-// CHECK-INST: mov z0.s, p6/m, za3h.s[w12, #0]
+mova z0.s, p6/m, za3h.s[w12, 0]
+// CHECK-INST: mov z0.s, p6/m, za3h.s[w12, 0]
// CHECK-ENCODING: [0x80,0x19,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 82 c0 <unknown>
-mova z17.s, p2/m, za0h.s[w14, #1]
-// CHECK-INST: mov z17.s, p2/m, za0h.s[w14, #1]
+mova z17.s, p2/m, za0h.s[w14, 1]
+// CHECK-INST: mov z17.s, p2/m, za0h.s[w14, 1]
// CHECK-ENCODING: [0x31,0x48,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 48 82 c0 <unknown>
-mova z29.s, p2/m, za1h.s[w12, #2]
-// CHECK-INST: mov z29.s, p2/m, za1h.s[w12, #2]
+mova z29.s, p2/m, za1h.s[w12, 2]
+// CHECK-INST: mov z29.s, p2/m, za1h.s[w12, 2]
// CHECK-ENCODING: [0xdd,0x08,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 08 82 c0 <unknown>
-mova z2.s, p5/m, za2h.s[w15, #1]
-// CHECK-INST: mov z2.s, p5/m, za2h.s[w15, #1]
+mova z2.s, p5/m, za2h.s[w15, 1]
+// CHECK-INST: mov z2.s, p5/m, za2h.s[w15, 1]
// CHECK-ENCODING: [0x22,0x75,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 82 c0 <unknown>
-mova z7.s, p2/m, za3h.s[w13, #0]
-// CHECK-INST: mov z7.s, p2/m, za3h.s[w13, #0]
+mova z7.s, p2/m, za3h.s[w13, 0]
+// CHECK-INST: mov z7.s, p2/m, za3h.s[w13, 0]
// CHECK-ENCODING: [0x87,0x29,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 82 c0 <unknown>
// Aliases
-mov z0.s, p0/m, za0h.s[w12, #0]
-// CHECK-INST: mov z0.s, p0/m, za0h.s[w12, #0]
+mov z0.s, p0/m, za0h.s[w12, 0]
+// CHECK-INST: mov z0.s, p0/m, za0h.s[w12, 0]
// CHECK-ENCODING: [0x00,0x00,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 82 c0 <unknown>
-mov z21.s, p5/m, za2h.s[w14, #2]
-// CHECK-INST: mov z21.s, p5/m, za2h.s[w14, #2]
+mov z21.s, p5/m, za2h.s[w14, 2]
+// CHECK-INST: mov z21.s, p5/m, za2h.s[w14, 2]
// CHECK-ENCODING: [0x55,0x55,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 55 82 c0 <unknown>
-mov z23.s, p3/m, za3h.s[w15, #1]
-// CHECK-INST: mov z23.s, p3/m, za3h.s[w15, #1]
+mov z23.s, p3/m, za3h.s[w15, 1]
+// CHECK-INST: mov z23.s, p3/m, za3h.s[w15, 1]
// CHECK-ENCODING: [0xb7,0x6d,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 6d 82 c0 <unknown>
-mov z31.s, p7/m, za3h.s[w15, #3]
-// CHECK-INST: mov z31.s, p7/m, za3h.s[w15, #3]
+mov z31.s, p7/m, za3h.s[w15, 3]
+// CHECK-INST: mov z31.s, p7/m, za3h.s[w15, 3]
// CHECK-ENCODING: [0xff,0x7d,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff 7d 82 c0 <unknown>
-mov z5.s, p3/m, za0h.s[w12, #1]
-// CHECK-INST: mov z5.s, p3/m, za0h.s[w12, #1]
+mov z5.s, p3/m, za0h.s[w12, 1]
+// CHECK-INST: mov z5.s, p3/m, za0h.s[w12, 1]
// CHECK-ENCODING: [0x25,0x0c,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0c 82 c0 <unknown>
-mov z1.s, p1/m, za0h.s[w12, #1]
-// CHECK-INST: mov z1.s, p1/m, za0h.s[w12, #1]
+mov z1.s, p1/m, za0h.s[w12, 1]
+// CHECK-INST: mov z1.s, p1/m, za0h.s[w12, 1]
// CHECK-ENCODING: [0x21,0x04,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 82 c0 <unknown>
-mov z24.s, p5/m, za0h.s[w14, #3]
-// CHECK-INST: mov z24.s, p5/m, za0h.s[w14, #3]
+mov z24.s, p5/m, za0h.s[w14, 3]
+// CHECK-INST: mov z24.s, p5/m, za0h.s[w14, 3]
// CHECK-ENCODING: [0x78,0x54,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 54 82 c0 <unknown>
-mov z0.s, p6/m, za3h.s[w12, #0]
-// CHECK-INST: mov z0.s, p6/m, za3h.s[w12, #0]
+mov z0.s, p6/m, za3h.s[w12, 0]
+// CHECK-INST: mov z0.s, p6/m, za3h.s[w12, 0]
// CHECK-ENCODING: [0x80,0x19,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 82 c0 <unknown>
-mov z17.s, p2/m, za0h.s[w14, #1]
-// CHECK-INST: mov z17.s, p2/m, za0h.s[w14, #1]
+mov z17.s, p2/m, za0h.s[w14, 1]
+// CHECK-INST: mov z17.s, p2/m, za0h.s[w14, 1]
// CHECK-ENCODING: [0x31,0x48,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 48 82 c0 <unknown>
-mov z29.s, p2/m, za1h.s[w12, #2]
-// CHECK-INST: mov z29.s, p2/m, za1h.s[w12, #2]
+mov z29.s, p2/m, za1h.s[w12, 2]
+// CHECK-INST: mov z29.s, p2/m, za1h.s[w12, 2]
// CHECK-ENCODING: [0xdd,0x08,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 08 82 c0 <unknown>
-mov z2.s, p5/m, za2h.s[w15, #1]
-// CHECK-INST: mov z2.s, p5/m, za2h.s[w15, #1]
+mov z2.s, p5/m, za2h.s[w15, 1]
+// CHECK-INST: mov z2.s, p5/m, za2h.s[w15, 1]
// CHECK-ENCODING: [0x22,0x75,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 82 c0 <unknown>
-mov z7.s, p2/m, za3h.s[w13, #0]
-// CHECK-INST: mov z7.s, p2/m, za3h.s[w13, #0]
+mov z7.s, p2/m, za3h.s[w13, 0]
+// CHECK-INST: mov z7.s, p2/m, za3h.s[w13, 0]
// CHECK-ENCODING: [0x87,0x29,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 82 c0 <unknown>
@@ -760,148 +760,148 @@ mov z7.s, p2/m, za3h.s[w13, #0]
// --------------------------------------------------------------------------//
// Extract, tile to vector, vertical, 32-bit
-mova z0.s, p0/m, za0v.s[w12, #0]
-// CHECK-INST: mov z0.s, p0/m, za0v.s[w12, #0]
+mova z0.s, p0/m, za0v.s[w12, 0]
+// CHECK-INST: mov z0.s, p0/m, za0v.s[w12, 0]
// CHECK-ENCODING: [0x00,0x80,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 82 c0 <unknown>
-mova z21.s, p5/m, za2v.s[w14, #2]
-// CHECK-INST: mov z21.s, p5/m, za2v.s[w14, #2]
+mova z21.s, p5/m, za2v.s[w14, 2]
+// CHECK-INST: mov z21.s, p5/m, za2v.s[w14, 2]
// CHECK-ENCODING: [0x55,0xd5,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 d5 82 c0 <unknown>
-mova z23.s, p3/m, za3v.s[w15, #1]
-// CHECK-INST: mov z23.s, p3/m, za3v.s[w15, #1]
+mova z23.s, p3/m, za3v.s[w15, 1]
+// CHECK-INST: mov z23.s, p3/m, za3v.s[w15, 1]
// CHECK-ENCODING: [0xb7,0xed,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 ed 82 c0 <unknown>
-mova z31.s, p7/m, za3v.s[w15, #3]
-// CHECK-INST: mov z31.s, p7/m, za3v.s[w15, #3]
+mova z31.s, p7/m, za3v.s[w15, 3]
+// CHECK-INST: mov z31.s, p7/m, za3v.s[w15, 3]
// CHECK-ENCODING: [0xff,0xfd,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff fd 82 c0 <unknown>
-mova z5.s, p3/m, za0v.s[w12, #1]
-// CHECK-INST: mov z5.s, p3/m, za0v.s[w12, #1]
+mova z5.s, p3/m, za0v.s[w12, 1]
+// CHECK-INST: mov z5.s, p3/m, za0v.s[w12, 1]
// CHECK-ENCODING: [0x25,0x8c,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8c 82 c0 <unknown>
-mova z1.s, p1/m, za0v.s[w12, #1]
-// CHECK-INST: mov z1.s, p1/m, za0v.s[w12, #1]
+mova z1.s, p1/m, za0v.s[w12, 1]
+// CHECK-INST: mov z1.s, p1/m, za0v.s[w12, 1]
// CHECK-ENCODING: [0x21,0x84,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 82 c0 <unknown>
-mova z24.s, p5/m, za0v.s[w14, #3]
-// CHECK-INST: mov z24.s, p5/m, za0v.s[w14, #3]
+mova z24.s, p5/m, za0v.s[w14, 3]
+// CHECK-INST: mov z24.s, p5/m, za0v.s[w14, 3]
// CHECK-ENCODING: [0x78,0xd4,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 d4 82 c0 <unknown>
-mova z0.s, p6/m, za3v.s[w12, #0]
-// CHECK-INST: mov z0.s, p6/m, za3v.s[w12, #0]
+mova z0.s, p6/m, za3v.s[w12, 0]
+// CHECK-INST: mov z0.s, p6/m, za3v.s[w12, 0]
// CHECK-ENCODING: [0x80,0x99,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 82 c0 <unknown>
-mova z17.s, p2/m, za0v.s[w14, #1]
-// CHECK-INST: mov z17.s, p2/m, za0v.s[w14, #1]
+mova z17.s, p2/m, za0v.s[w14, 1]
+// CHECK-INST: mov z17.s, p2/m, za0v.s[w14, 1]
// CHECK-ENCODING: [0x31,0xc8,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 c8 82 c0 <unknown>
-mova z29.s, p2/m, za1v.s[w12, #2]
-// CHECK-INST: mov z29.s, p2/m, za1v.s[w12, #2]
+mova z29.s, p2/m, za1v.s[w12, 2]
+// CHECK-INST: mov z29.s, p2/m, za1v.s[w12, 2]
// CHECK-ENCODING: [0xdd,0x88,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 88 82 c0 <unknown>
-mova z2.s, p5/m, za2v.s[w15, #1]
-// CHECK-INST: mov z2.s, p5/m, za2v.s[w15, #1]
+mova z2.s, p5/m, za2v.s[w15, 1]
+// CHECK-INST: mov z2.s, p5/m, za2v.s[w15, 1]
// CHECK-ENCODING: [0x22,0xf5,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 82 c0 <unknown>
-mova z7.s, p2/m, za3v.s[w13, #0]
-// CHECK-INST: mov z7.s, p2/m, za3v.s[w13, #0]
+mova z7.s, p2/m, za3v.s[w13, 0]
+// CHECK-INST: mov z7.s, p2/m, za3v.s[w13, 0]
// CHECK-ENCODING: [0x87,0xa9,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 82 c0 <unknown>
// Aliases
-mov z0.s, p0/m, za0v.s[w12, #0]
-// CHECK-INST: mov z0.s, p0/m, za0v.s[w12, #0]
+mov z0.s, p0/m, za0v.s[w12, 0]
+// CHECK-INST: mov z0.s, p0/m, za0v.s[w12, 0]
// CHECK-ENCODING: [0x00,0x80,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 82 c0 <unknown>
-mov z21.s, p5/m, za2v.s[w14, #2]
-// CHECK-INST: mov z21.s, p5/m, za2v.s[w14, #2]
+mov z21.s, p5/m, za2v.s[w14, 2]
+// CHECK-INST: mov z21.s, p5/m, za2v.s[w14, 2]
// CHECK-ENCODING: [0x55,0xd5,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 d5 82 c0 <unknown>
-mov z23.s, p3/m, za3v.s[w15, #1]
-// CHECK-INST: mov z23.s, p3/m, za3v.s[w15, #1]
+mov z23.s, p3/m, za3v.s[w15, 1]
+// CHECK-INST: mov z23.s, p3/m, za3v.s[w15, 1]
// CHECK-ENCODING: [0xb7,0xed,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 ed 82 c0 <unknown>
-mov z31.s, p7/m, za3v.s[w15, #3]
-// CHECK-INST: mov z31.s, p7/m, za3v.s[w15, #3]
+mov z31.s, p7/m, za3v.s[w15, 3]
+// CHECK-INST: mov z31.s, p7/m, za3v.s[w15, 3]
// CHECK-ENCODING: [0xff,0xfd,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff fd 82 c0 <unknown>
-mov z5.s, p3/m, za0v.s[w12, #1]
-// CHECK-INST: mov z5.s, p3/m, za0v.s[w12, #1]
+mov z5.s, p3/m, za0v.s[w12, 1]
+// CHECK-INST: mov z5.s, p3/m, za0v.s[w12, 1]
// CHECK-ENCODING: [0x25,0x8c,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8c 82 c0 <unknown>
-mov z1.s, p1/m, za0v.s[w12, #1]
-// CHECK-INST: mov z1.s, p1/m, za0v.s[w12, #1]
+mov z1.s, p1/m, za0v.s[w12, 1]
+// CHECK-INST: mov z1.s, p1/m, za0v.s[w12, 1]
// CHECK-ENCODING: [0x21,0x84,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 82 c0 <unknown>
-mov z24.s, p5/m, za0v.s[w14, #3]
-// CHECK-INST: mov z24.s, p5/m, za0v.s[w14, #3]
+mov z24.s, p5/m, za0v.s[w14, 3]
+// CHECK-INST: mov z24.s, p5/m, za0v.s[w14, 3]
// CHECK-ENCODING: [0x78,0xd4,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 d4 82 c0 <unknown>
-mov z0.s, p6/m, za3v.s[w12, #0]
-// CHECK-INST: mov z0.s, p6/m, za3v.s[w12, #0]
+mov z0.s, p6/m, za3v.s[w12, 0]
+// CHECK-INST: mov z0.s, p6/m, za3v.s[w12, 0]
// CHECK-ENCODING: [0x80,0x99,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 82 c0 <unknown>
-mov z17.s, p2/m, za0v.s[w14, #1]
-// CHECK-INST: mov z17.s, p2/m, za0v.s[w14, #1]
+mov z17.s, p2/m, za0v.s[w14, 1]
+// CHECK-INST: mov z17.s, p2/m, za0v.s[w14, 1]
// CHECK-ENCODING: [0x31,0xc8,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 c8 82 c0 <unknown>
-mov z29.s, p2/m, za1v.s[w12, #2]
-// CHECK-INST: mov z29.s, p2/m, za1v.s[w12, #2]
+mov z29.s, p2/m, za1v.s[w12, 2]
+// CHECK-INST: mov z29.s, p2/m, za1v.s[w12, 2]
// CHECK-ENCODING: [0xdd,0x88,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 88 82 c0 <unknown>
-mov z2.s, p5/m, za2v.s[w15, #1]
-// CHECK-INST: mov z2.s, p5/m, za2v.s[w15, #1]
+mov z2.s, p5/m, za2v.s[w15, 1]
+// CHECK-INST: mov z2.s, p5/m, za2v.s[w15, 1]
// CHECK-ENCODING: [0x22,0xf5,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 82 c0 <unknown>
-mov z7.s, p2/m, za3v.s[w13, #0]
-// CHECK-INST: mov z7.s, p2/m, za3v.s[w13, #0]
+mov z7.s, p2/m, za3v.s[w13, 0]
+// CHECK-INST: mov z7.s, p2/m, za3v.s[w13, 0]
// CHECK-ENCODING: [0x87,0xa9,0x82,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 82 c0 <unknown>
@@ -909,148 +909,148 @@ mov z7.s, p2/m, za3v.s[w13, #0]
// --------------------------------------------------------------------------//
// Extract, tile to vector, horizontal, 64-bit
-mova z0.d, p0/m, za0h.d[w12, #0]
-// CHECK-INST: mov z0.d, p0/m, za0h.d[w12, #0]
+mova z0.d, p0/m, za0h.d[w12, 0]
+// CHECK-INST: mov z0.d, p0/m, za0h.d[w12, 0]
// CHECK-ENCODING: [0x00,0x00,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 c2 c0 <unknown>
-mova z21.d, p5/m, za5h.d[w14, #0]
-// CHECK-INST: mov z21.d, p5/m, za5h.d[w14, #0]
+mova z21.d, p5/m, za5h.d[w14, 0]
+// CHECK-INST: mov z21.d, p5/m, za5h.d[w14, 0]
// CHECK-ENCODING: [0x55,0x55,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 55 c2 c0 <unknown>
-mova z23.d, p3/m, za6h.d[w15, #1]
-// CHECK-INST: mov z23.d, p3/m, za6h.d[w15, #1]
+mova z23.d, p3/m, za6h.d[w15, 1]
+// CHECK-INST: mov z23.d, p3/m, za6h.d[w15, 1]
// CHECK-ENCODING: [0xb7,0x6d,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 6d c2 c0 <unknown>
-mova z31.d, p7/m, za7h.d[w15, #1]
-// CHECK-INST: mov z31.d, p7/m, za7h.d[w15, #1]
+mova z31.d, p7/m, za7h.d[w15, 1]
+// CHECK-INST: mov z31.d, p7/m, za7h.d[w15, 1]
// CHECK-ENCODING: [0xff,0x7d,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff 7d c2 c0 <unknown>
-mova z5.d, p3/m, za0h.d[w12, #1]
-// CHECK-INST: mov z5.d, p3/m, za0h.d[w12, #1]
+mova z5.d, p3/m, za0h.d[w12, 1]
+// CHECK-INST: mov z5.d, p3/m, za0h.d[w12, 1]
// CHECK-ENCODING: [0x25,0x0c,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0c c2 c0 <unknown>
-mova z1.d, p1/m, za0h.d[w12, #1]
-// CHECK-INST: mov z1.d, p1/m, za0h.d[w12, #1]
+mova z1.d, p1/m, za0h.d[w12, 1]
+// CHECK-INST: mov z1.d, p1/m, za0h.d[w12, 1]
// CHECK-ENCODING: [0x21,0x04,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 c2 c0 <unknown>
-mova z24.d, p5/m, za1h.d[w14, #1]
-// CHECK-INST: mov z24.d, p5/m, za1h.d[w14, #1]
+mova z24.d, p5/m, za1h.d[w14, 1]
+// CHECK-INST: mov z24.d, p5/m, za1h.d[w14, 1]
// CHECK-ENCODING: [0x78,0x54,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 54 c2 c0 <unknown>
-mova z0.d, p6/m, za6h.d[w12, #0]
-// CHECK-INST: mov z0.d, p6/m, za6h.d[w12, #0]
+mova z0.d, p6/m, za6h.d[w12, 0]
+// CHECK-INST: mov z0.d, p6/m, za6h.d[w12, 0]
// CHECK-ENCODING: [0x80,0x19,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 c2 c0 <unknown>
-mova z17.d, p2/m, za0h.d[w14, #1]
-// CHECK-INST: mov z17.d, p2/m, za0h.d[w14, #1]
+mova z17.d, p2/m, za0h.d[w14, 1]
+// CHECK-INST: mov z17.d, p2/m, za0h.d[w14, 1]
// CHECK-ENCODING: [0x31,0x48,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 48 c2 c0 <unknown>
-mova z29.d, p2/m, za3h.d[w12, #0]
-// CHECK-INST: mov z29.d, p2/m, za3h.d[w12, #0]
+mova z29.d, p2/m, za3h.d[w12, 0]
+// CHECK-INST: mov z29.d, p2/m, za3h.d[w12, 0]
// CHECK-ENCODING: [0xdd,0x08,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 08 c2 c0 <unknown>
-mova z2.d, p5/m, za4h.d[w15, #1]
-// CHECK-INST: mov z2.d, p5/m, za4h.d[w15, #1]
+mova z2.d, p5/m, za4h.d[w15, 1]
+// CHECK-INST: mov z2.d, p5/m, za4h.d[w15, 1]
// CHECK-ENCODING: [0x22,0x75,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 c2 c0 <unknown>
-mova z7.d, p2/m, za6h.d[w13, #0]
-// CHECK-INST: mov z7.d, p2/m, za6h.d[w13, #0]
+mova z7.d, p2/m, za6h.d[w13, 0]
+// CHECK-INST: mov z7.d, p2/m, za6h.d[w13, 0]
// CHECK-ENCODING: [0x87,0x29,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 c2 c0 <unknown>
// Aliases
-mov z0.d, p0/m, za0h.d[w12, #0]
-// CHECK-INST: mov z0.d, p0/m, za0h.d[w12, #0]
+mov z0.d, p0/m, za0h.d[w12, 0]
+// CHECK-INST: mov z0.d, p0/m, za0h.d[w12, 0]
// CHECK-ENCODING: [0x00,0x00,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 c2 c0 <unknown>
-mov z21.d, p5/m, za5h.d[w14, #0]
-// CHECK-INST: mov z21.d, p5/m, za5h.d[w14, #0]
+mov z21.d, p5/m, za5h.d[w14, 0]
+// CHECK-INST: mov z21.d, p5/m, za5h.d[w14, 0]
// CHECK-ENCODING: [0x55,0x55,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 55 c2 c0 <unknown>
-mov z23.d, p3/m, za6h.d[w15, #1]
-// CHECK-INST: mov z23.d, p3/m, za6h.d[w15, #1]
+mov z23.d, p3/m, za6h.d[w15, 1]
+// CHECK-INST: mov z23.d, p3/m, za6h.d[w15, 1]
// CHECK-ENCODING: [0xb7,0x6d,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 6d c2 c0 <unknown>
-mov z31.d, p7/m, za7h.d[w15, #1]
-// CHECK-INST: mov z31.d, p7/m, za7h.d[w15, #1]
+mov z31.d, p7/m, za7h.d[w15, 1]
+// CHECK-INST: mov z31.d, p7/m, za7h.d[w15, 1]
// CHECK-ENCODING: [0xff,0x7d,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff 7d c2 c0 <unknown>
-mov z5.d, p3/m, za0h.d[w12, #1]
-// CHECK-INST: mov z5.d, p3/m, za0h.d[w12, #1]
+mov z5.d, p3/m, za0h.d[w12, 1]
+// CHECK-INST: mov z5.d, p3/m, za0h.d[w12, 1]
// CHECK-ENCODING: [0x25,0x0c,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0c c2 c0 <unknown>
-mov z1.d, p1/m, za0h.d[w12, #1]
-// CHECK-INST: mov z1.d, p1/m, za0h.d[w12, #1]
+mov z1.d, p1/m, za0h.d[w12, 1]
+// CHECK-INST: mov z1.d, p1/m, za0h.d[w12, 1]
// CHECK-ENCODING: [0x21,0x04,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 c2 c0 <unknown>
-mov z24.d, p5/m, za1h.d[w14, #1]
-// CHECK-INST: mov z24.d, p5/m, za1h.d[w14, #1]
+mov z24.d, p5/m, za1h.d[w14, 1]
+// CHECK-INST: mov z24.d, p5/m, za1h.d[w14, 1]
// CHECK-ENCODING: [0x78,0x54,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 54 c2 c0 <unknown>
-mov z0.d, p6/m, za6h.d[w12, #0]
-// CHECK-INST: mov z0.d, p6/m, za6h.d[w12, #0]
+mov z0.d, p6/m, za6h.d[w12, 0]
+// CHECK-INST: mov z0.d, p6/m, za6h.d[w12, 0]
// CHECK-ENCODING: [0x80,0x19,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 c2 c0 <unknown>
-mov z17.d, p2/m, za0h.d[w14, #1]
-// CHECK-INST: mov z17.d, p2/m, za0h.d[w14, #1]
+mov z17.d, p2/m, za0h.d[w14, 1]
+// CHECK-INST: mov z17.d, p2/m, za0h.d[w14, 1]
// CHECK-ENCODING: [0x31,0x48,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 48 c2 c0 <unknown>
-mov z29.d, p2/m, za3h.d[w12, #0]
-// CHECK-INST: mov z29.d, p2/m, za3h.d[w12, #0]
+mov z29.d, p2/m, za3h.d[w12, 0]
+// CHECK-INST: mov z29.d, p2/m, za3h.d[w12, 0]
// CHECK-ENCODING: [0xdd,0x08,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 08 c2 c0 <unknown>
-mov z2.d, p5/m, za4h.d[w15, #1]
-// CHECK-INST: mov z2.d, p5/m, za4h.d[w15, #1]
+mov z2.d, p5/m, za4h.d[w15, 1]
+// CHECK-INST: mov z2.d, p5/m, za4h.d[w15, 1]
// CHECK-ENCODING: [0x22,0x75,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 c2 c0 <unknown>
-mov z7.d, p2/m, za6h.d[w13, #0]
-// CHECK-INST: mov z7.d, p2/m, za6h.d[w13, #0]
+mov z7.d, p2/m, za6h.d[w13, 0]
+// CHECK-INST: mov z7.d, p2/m, za6h.d[w13, 0]
// CHECK-ENCODING: [0x87,0x29,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 c2 c0 <unknown>
@@ -1058,148 +1058,148 @@ mov z7.d, p2/m, za6h.d[w13, #0]
// --------------------------------------------------------------------------//
// Extract, tile to vector, vertical, 64-bit
-mova z0.d, p0/m, za0v.d[w12, #0]
-// CHECK-INST: mov z0.d, p0/m, za0v.d[w12, #0]
+mova z0.d, p0/m, za0v.d[w12, 0]
+// CHECK-INST: mov z0.d, p0/m, za0v.d[w12, 0]
// CHECK-ENCODING: [0x00,0x80,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 c2 c0 <unknown>
-mova z21.d, p5/m, za5v.d[w14, #0]
-// CHECK-INST: mov z21.d, p5/m, za5v.d[w14, #0]
+mova z21.d, p5/m, za5v.d[w14, 0]
+// CHECK-INST: mov z21.d, p5/m, za5v.d[w14, 0]
// CHECK-ENCODING: [0x55,0xd5,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 d5 c2 c0 <unknown>
-mova z23.d, p3/m, za6v.d[w15, #1]
-// CHECK-INST: mov z23.d, p3/m, za6v.d[w15, #1]
+mova z23.d, p3/m, za6v.d[w15, 1]
+// CHECK-INST: mov z23.d, p3/m, za6v.d[w15, 1]
// CHECK-ENCODING: [0xb7,0xed,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 ed c2 c0 <unknown>
-mova z31.d, p7/m, za7v.d[w15, #1]
-// CHECK-INST: mov z31.d, p7/m, za7v.d[w15, #1]
+mova z31.d, p7/m, za7v.d[w15, 1]
+// CHECK-INST: mov z31.d, p7/m, za7v.d[w15, 1]
// CHECK-ENCODING: [0xff,0xfd,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff fd c2 c0 <unknown>
-mova z5.d, p3/m, za0v.d[w12, #1]
-// CHECK-INST: mov z5.d, p3/m, za0v.d[w12, #1]
+mova z5.d, p3/m, za0v.d[w12, 1]
+// CHECK-INST: mov z5.d, p3/m, za0v.d[w12, 1]
// CHECK-ENCODING: [0x25,0x8c,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8c c2 c0 <unknown>
-mova z1.d, p1/m, za0v.d[w12, #1]
-// CHECK-INST: mov z1.d, p1/m, za0v.d[w12, #1]
+mova z1.d, p1/m, za0v.d[w12, 1]
+// CHECK-INST: mov z1.d, p1/m, za0v.d[w12, 1]
// CHECK-ENCODING: [0x21,0x84,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 c2 c0 <unknown>
-mova z24.d, p5/m, za1v.d[w14, #1]
-// CHECK-INST: mov z24.d, p5/m, za1v.d[w14, #1]
+mova z24.d, p5/m, za1v.d[w14, 1]
+// CHECK-INST: mov z24.d, p5/m, za1v.d[w14, 1]
// CHECK-ENCODING: [0x78,0xd4,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 d4 c2 c0 <unknown>
-mova z0.d, p6/m, za6v.d[w12, #0]
-// CHECK-INST: mov z0.d, p6/m, za6v.d[w12, #0]
+mova z0.d, p6/m, za6v.d[w12, 0]
+// CHECK-INST: mov z0.d, p6/m, za6v.d[w12, 0]
// CHECK-ENCODING: [0x80,0x99,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 c2 c0 <unknown>
-mova z17.d, p2/m, za0v.d[w14, #1]
-// CHECK-INST: mov z17.d, p2/m, za0v.d[w14, #1]
+mova z17.d, p2/m, za0v.d[w14, 1]
+// CHECK-INST: mov z17.d, p2/m, za0v.d[w14, 1]
// CHECK-ENCODING: [0x31,0xc8,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 c8 c2 c0 <unknown>
-mova z29.d, p2/m, za3v.d[w12, #0]
-// CHECK-INST: mov z29.d, p2/m, za3v.d[w12, #0]
+mova z29.d, p2/m, za3v.d[w12, 0]
+// CHECK-INST: mov z29.d, p2/m, za3v.d[w12, 0]
// CHECK-ENCODING: [0xdd,0x88,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 88 c2 c0 <unknown>
-mova z2.d, p5/m, za4v.d[w15, #1]
-// CHECK-INST: mov z2.d, p5/m, za4v.d[w15, #1]
+mova z2.d, p5/m, za4v.d[w15, 1]
+// CHECK-INST: mov z2.d, p5/m, za4v.d[w15, 1]
// CHECK-ENCODING: [0x22,0xf5,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 c2 c0 <unknown>
-mova z7.d, p2/m, za6v.d[w13, #0]
-// CHECK-INST: mov z7.d, p2/m, za6v.d[w13, #0]
+mova z7.d, p2/m, za6v.d[w13, 0]
+// CHECK-INST: mov z7.d, p2/m, za6v.d[w13, 0]
// CHECK-ENCODING: [0x87,0xa9,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 c2 c0 <unknown>
// Aliases
-mov z0.d, p0/m, za0v.d[w12, #0]
-// CHECK-INST: mov z0.d, p0/m, za0v.d[w12, #0]
+mov z0.d, p0/m, za0v.d[w12, 0]
+// CHECK-INST: mov z0.d, p0/m, za0v.d[w12, 0]
// CHECK-ENCODING: [0x00,0x80,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 c2 c0 <unknown>
-mov z21.d, p5/m, za5v.d[w14, #0]
-// CHECK-INST: mov z21.d, p5/m, za5v.d[w14, #0]
+mov z21.d, p5/m, za5v.d[w14, 0]
+// CHECK-INST: mov z21.d, p5/m, za5v.d[w14, 0]
// CHECK-ENCODING: [0x55,0xd5,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 d5 c2 c0 <unknown>
-mov z23.d, p3/m, za6v.d[w15, #1]
-// CHECK-INST: mov z23.d, p3/m, za6v.d[w15, #1]
+mov z23.d, p3/m, za6v.d[w15, 1]
+// CHECK-INST: mov z23.d, p3/m, za6v.d[w15, 1]
// CHECK-ENCODING: [0xb7,0xed,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 ed c2 c0 <unknown>
-mov z31.d, p7/m, za7v.d[w15, #1]
-// CHECK-INST: mov z31.d, p7/m, za7v.d[w15, #1]
+mov z31.d, p7/m, za7v.d[w15, 1]
+// CHECK-INST: mov z31.d, p7/m, za7v.d[w15, 1]
// CHECK-ENCODING: [0xff,0xfd,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff fd c2 c0 <unknown>
-mov z5.d, p3/m, za0v.d[w12, #1]
-// CHECK-INST: mov z5.d, p3/m, za0v.d[w12, #1]
+mov z5.d, p3/m, za0v.d[w12, 1]
+// CHECK-INST: mov z5.d, p3/m, za0v.d[w12, 1]
// CHECK-ENCODING: [0x25,0x8c,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8c c2 c0 <unknown>
-mov z1.d, p1/m, za0v.d[w12, #1]
-// CHECK-INST: mov z1.d, p1/m, za0v.d[w12, #1]
+mov z1.d, p1/m, za0v.d[w12, 1]
+// CHECK-INST: mov z1.d, p1/m, za0v.d[w12, 1]
// CHECK-ENCODING: [0x21,0x84,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 c2 c0 <unknown>
-mov z24.d, p5/m, za1v.d[w14, #1]
-// CHECK-INST: mov z24.d, p5/m, za1v.d[w14, #1]
+mov z24.d, p5/m, za1v.d[w14, 1]
+// CHECK-INST: mov z24.d, p5/m, za1v.d[w14, 1]
// CHECK-ENCODING: [0x78,0xd4,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 d4 c2 c0 <unknown>
-mov z0.d, p6/m, za6v.d[w12, #0]
-// CHECK-INST: mov z0.d, p6/m, za6v.d[w12, #0]
+mov z0.d, p6/m, za6v.d[w12, 0]
+// CHECK-INST: mov z0.d, p6/m, za6v.d[w12, 0]
// CHECK-ENCODING: [0x80,0x99,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 c2 c0 <unknown>
-mov z17.d, p2/m, za0v.d[w14, #1]
-// CHECK-INST: mov z17.d, p2/m, za0v.d[w14, #1]
+mov z17.d, p2/m, za0v.d[w14, 1]
+// CHECK-INST: mov z17.d, p2/m, za0v.d[w14, 1]
// CHECK-ENCODING: [0x31,0xc8,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 c8 c2 c0 <unknown>
-mov z29.d, p2/m, za3v.d[w12, #0]
-// CHECK-INST: mov z29.d, p2/m, za3v.d[w12, #0]
+mov z29.d, p2/m, za3v.d[w12, 0]
+// CHECK-INST: mov z29.d, p2/m, za3v.d[w12, 0]
// CHECK-ENCODING: [0xdd,0x88,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 88 c2 c0 <unknown>
-mov z2.d, p5/m, za4v.d[w15, #1]
-// CHECK-INST: mov z2.d, p5/m, za4v.d[w15, #1]
+mov z2.d, p5/m, za4v.d[w15, 1]
+// CHECK-INST: mov z2.d, p5/m, za4v.d[w15, 1]
// CHECK-ENCODING: [0x22,0xf5,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 c2 c0 <unknown>
-mov z7.d, p2/m, za6v.d[w13, #0]
-// CHECK-INST: mov z7.d, p2/m, za6v.d[w13, #0]
+mov z7.d, p2/m, za6v.d[w13, 0]
+// CHECK-INST: mov z7.d, p2/m, za6v.d[w13, 0]
// CHECK-ENCODING: [0x87,0xa9,0xc2,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 c2 c0 <unknown>
@@ -1207,148 +1207,148 @@ mov z7.d, p2/m, za6v.d[w13, #0]
// --------------------------------------------------------------------------//
// Extract, tile to vector, horizontal, 128-bit
-mova z0.q, p0/m, za0h.q[w12]
-// CHECK-INST: mov z0.q, p0/m, za0h.q[w12]
+mova z0.q, p0/m, za0h.q[w12, 0]
+// CHECK-INST: mov z0.q, p0/m, za0h.q[w12, 0]
// CHECK-ENCODING: [0x00,0x00,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 c3 c0 <unknown>
-mova z21.q, p5/m, za10h.q[w14]
-// CHECK-INST: mov z21.q, p5/m, za10h.q[w14]
+mova z21.q, p5/m, za10h.q[w14, 0]
+// CHECK-INST: mov z21.q, p5/m, za10h.q[w14, 0]
// CHECK-ENCODING: [0x55,0x55,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 55 c3 c0 <unknown>
-mova z23.q, p3/m, za13h.q[w15]
-// CHECK-INST: mov z23.q, p3/m, za13h.q[w15]
+mova z23.q, p3/m, za13h.q[w15, 0]
+// CHECK-INST: mov z23.q, p3/m, za13h.q[w15, 0]
// CHECK-ENCODING: [0xb7,0x6d,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 6d c3 c0 <unknown>
-mova z31.q, p7/m, za15h.q[w15]
-// CHECK-INST: mov z31.q, p7/m, za15h.q[w15]
+mova z31.q, p7/m, za15h.q[w15, 0]
+// CHECK-INST: mov z31.q, p7/m, za15h.q[w15, 0]
// CHECK-ENCODING: [0xff,0x7d,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff 7d c3 c0 <unknown>
-mova z5.q, p3/m, za1h.q[w12]
-// CHECK-INST: mov z5.q, p3/m, za1h.q[w12]
+mova z5.q, p3/m, za1h.q[w12, 0]
+// CHECK-INST: mov z5.q, p3/m, za1h.q[w12, 0]
// CHECK-ENCODING: [0x25,0x0c,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0c c3 c0 <unknown>
-mova z1.q, p1/m, za1h.q[w12]
-// CHECK-INST: mov z1.q, p1/m, za1h.q[w12]
+mova z1.q, p1/m, za1h.q[w12, 0]
+// CHECK-INST: mov z1.q, p1/m, za1h.q[w12, 0]
// CHECK-ENCODING: [0x21,0x04,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 c3 c0 <unknown>
-mova z24.q, p5/m, za3h.q[w14]
-// CHECK-INST: mov z24.q, p5/m, za3h.q[w14]
+mova z24.q, p5/m, za3h.q[w14, 0]
+// CHECK-INST: mov z24.q, p5/m, za3h.q[w14, 0]
// CHECK-ENCODING: [0x78,0x54,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 54 c3 c0 <unknown>
-mova z0.q, p6/m, za12h.q[w12]
-// CHECK-INST: mov z0.q, p6/m, za12h.q[w12]
+mova z0.q, p6/m, za12h.q[w12, 0]
+// CHECK-INST: mov z0.q, p6/m, za12h.q[w12, 0]
// CHECK-ENCODING: [0x80,0x19,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 c3 c0 <unknown>
-mova z17.q, p2/m, za1h.q[w14]
-// CHECK-INST: mov z17.q, p2/m, za1h.q[w14]
+mova z17.q, p2/m, za1h.q[w14, 0]
+// CHECK-INST: mov z17.q, p2/m, za1h.q[w14, 0]
// CHECK-ENCODING: [0x31,0x48,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 48 c3 c0 <unknown>
-mova z29.q, p2/m, za6h.q[w12]
-// CHECK-INST: mov z29.q, p2/m, za6h.q[w12]
+mova z29.q, p2/m, za6h.q[w12, 0]
+// CHECK-INST: mov z29.q, p2/m, za6h.q[w12, 0]
// CHECK-ENCODING: [0xdd,0x08,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 08 c3 c0 <unknown>
-mova z2.q, p5/m, za9h.q[w15]
-// CHECK-INST: mov z2.q, p5/m, za9h.q[w15]
+mova z2.q, p5/m, za9h.q[w15, 0]
+// CHECK-INST: mov z2.q, p5/m, za9h.q[w15, 0]
// CHECK-ENCODING: [0x22,0x75,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 c3 c0 <unknown>
-mova z7.q, p2/m, za12h.q[w13]
-// CHECK-INST: mov z7.q, p2/m, za12h.q[w13]
+mova z7.q, p2/m, za12h.q[w13, 0]
+// CHECK-INST: mov z7.q, p2/m, za12h.q[w13, 0]
// CHECK-ENCODING: [0x87,0x29,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 c3 c0 <unknown>
// Aliases
-mov z0.q, p0/m, za0h.q[w12]
-// CHECK-INST: mov z0.q, p0/m, za0h.q[w12]
+mov z0.q, p0/m, za0h.q[w12, 0]
+// CHECK-INST: mov z0.q, p0/m, za0h.q[w12, 0]
// CHECK-ENCODING: [0x00,0x00,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 c3 c0 <unknown>
-mov z21.q, p5/m, za10h.q[w14]
-// CHECK-INST: mov z21.q, p5/m, za10h.q[w14]
+mov z21.q, p5/m, za10h.q[w14, 0]
+// CHECK-INST: mov z21.q, p5/m, za10h.q[w14, 0]
// CHECK-ENCODING: [0x55,0x55,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 55 c3 c0 <unknown>
-mov z23.q, p3/m, za13h.q[w15]
-// CHECK-INST: mov z23.q, p3/m, za13h.q[w15]
+mov z23.q, p3/m, za13h.q[w15, 0]
+// CHECK-INST: mov z23.q, p3/m, za13h.q[w15, 0]
// CHECK-ENCODING: [0xb7,0x6d,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 6d c3 c0 <unknown>
-mov z31.q, p7/m, za15h.q[w15]
-// CHECK-INST: mov z31.q, p7/m, za15h.q[w15]
+mov z31.q, p7/m, za15h.q[w15, 0]
+// CHECK-INST: mov z31.q, p7/m, za15h.q[w15, 0]
// CHECK-ENCODING: [0xff,0x7d,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff 7d c3 c0 <unknown>
-mov z5.q, p3/m, za1h.q[w12]
-// CHECK-INST: mov z5.q, p3/m, za1h.q[w12]
+mov z5.q, p3/m, za1h.q[w12, 0]
+// CHECK-INST: mov z5.q, p3/m, za1h.q[w12, 0]
// CHECK-ENCODING: [0x25,0x0c,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0c c3 c0 <unknown>
-mov z1.q, p1/m, za1h.q[w12]
-// CHECK-INST: mov z1.q, p1/m, za1h.q[w12]
+mov z1.q, p1/m, za1h.q[w12, 0]
+// CHECK-INST: mov z1.q, p1/m, za1h.q[w12, 0]
// CHECK-ENCODING: [0x21,0x04,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 c3 c0 <unknown>
-mov z24.q, p5/m, za3h.q[w14]
-// CHECK-INST: mov z24.q, p5/m, za3h.q[w14]
+mov z24.q, p5/m, za3h.q[w14, 0]
+// CHECK-INST: mov z24.q, p5/m, za3h.q[w14, 0]
// CHECK-ENCODING: [0x78,0x54,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 54 c3 c0 <unknown>
-mov z0.q, p6/m, za12h.q[w12]
-// CHECK-INST: mov z0.q, p6/m, za12h.q[w12]
+mov z0.q, p6/m, za12h.q[w12, 0]
+// CHECK-INST: mov z0.q, p6/m, za12h.q[w12, 0]
// CHECK-ENCODING: [0x80,0x19,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 c3 c0 <unknown>
-mov z17.q, p2/m, za1h.q[w14]
-// CHECK-INST: mov z17.q, p2/m, za1h.q[w14]
+mov z17.q, p2/m, za1h.q[w14, 0]
+// CHECK-INST: mov z17.q, p2/m, za1h.q[w14, 0]
// CHECK-ENCODING: [0x31,0x48,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 48 c3 c0 <unknown>
-mov z29.q, p2/m, za6h.q[w12]
-// CHECK-INST: mov z29.q, p2/m, za6h.q[w12]
+mov z29.q, p2/m, za6h.q[w12, 0]
+// CHECK-INST: mov z29.q, p2/m, za6h.q[w12, 0]
// CHECK-ENCODING: [0xdd,0x08,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 08 c3 c0 <unknown>
-mov z2.q, p5/m, za9h.q[w15]
-// CHECK-INST: mov z2.q, p5/m, za9h.q[w15]
+mov z2.q, p5/m, za9h.q[w15, 0]
+// CHECK-INST: mov z2.q, p5/m, za9h.q[w15, 0]
// CHECK-ENCODING: [0x22,0x75,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 c3 c0 <unknown>
-mov z7.q, p2/m, za12h.q[w13]
-// CHECK-INST: mov z7.q, p2/m, za12h.q[w13]
+mov z7.q, p2/m, za12h.q[w13, 0]
+// CHECK-INST: mov z7.q, p2/m, za12h.q[w13, 0]
// CHECK-ENCODING: [0x87,0x29,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 c3 c0 <unknown>
@@ -1356,148 +1356,148 @@ mov z7.q, p2/m, za12h.q[w13]
// --------------------------------------------------------------------------//
// Extract, tile to vector, vertical, 128-bit
-mova z0.q, p0/m, za0v.q[w12]
-// CHECK-INST: mov z0.q, p0/m, za0v.q[w12]
+mova z0.q, p0/m, za0v.q[w12, 0]
+// CHECK-INST: mov z0.q, p0/m, za0v.q[w12, 0]
// CHECK-ENCODING: [0x00,0x80,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 c3 c0 <unknown>
-mova z21.q, p5/m, za10v.q[w14]
-// CHECK-INST: mov z21.q, p5/m, za10v.q[w14]
+mova z21.q, p5/m, za10v.q[w14, 0]
+// CHECK-INST: mov z21.q, p5/m, za10v.q[w14, 0]
// CHECK-ENCODING: [0x55,0xd5,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 d5 c3 c0 <unknown>
-mova z23.q, p3/m, za13v.q[w15]
-// CHECK-INST: mov z23.q, p3/m, za13v.q[w15]
+mova z23.q, p3/m, za13v.q[w15, 0]
+// CHECK-INST: mov z23.q, p3/m, za13v.q[w15, 0]
// CHECK-ENCODING: [0xb7,0xed,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 ed c3 c0 <unknown>
-mova z31.q, p7/m, za15v.q[w15]
-// CHECK-INST: mov z31.q, p7/m, za15v.q[w15]
+mova z31.q, p7/m, za15v.q[w15, 0]
+// CHECK-INST: mov z31.q, p7/m, za15v.q[w15, 0]
// CHECK-ENCODING: [0xff,0xfd,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff fd c3 c0 <unknown>
-mova z5.q, p3/m, za1v.q[w12]
-// CHECK-INST: mov z5.q, p3/m, za1v.q[w12]
+mova z5.q, p3/m, za1v.q[w12, 0]
+// CHECK-INST: mov z5.q, p3/m, za1v.q[w12, 0]
// CHECK-ENCODING: [0x25,0x8c,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8c c3 c0 <unknown>
-mova z1.q, p1/m, za1v.q[w12]
-// CHECK-INST: mov z1.q, p1/m, za1v.q[w12]
+mova z1.q, p1/m, za1v.q[w12, 0]
+// CHECK-INST: mov z1.q, p1/m, za1v.q[w12, 0]
// CHECK-ENCODING: [0x21,0x84,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 c3 c0 <unknown>
-mova z24.q, p5/m, za3v.q[w14]
-// CHECK-INST: mov z24.q, p5/m, za3v.q[w14]
+mova z24.q, p5/m, za3v.q[w14, 0]
+// CHECK-INST: mov z24.q, p5/m, za3v.q[w14, 0]
// CHECK-ENCODING: [0x78,0xd4,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 d4 c3 c0 <unknown>
-mova z0.q, p6/m, za12v.q[w12]
-// CHECK-INST: mov z0.q, p6/m, za12v.q[w12]
+mova z0.q, p6/m, za12v.q[w12, 0]
+// CHECK-INST: mov z0.q, p6/m, za12v.q[w12, 0]
// CHECK-ENCODING: [0x80,0x99,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 c3 c0 <unknown>
-mova z17.q, p2/m, za1v.q[w14]
-// CHECK-INST: mov z17.q, p2/m, za1v.q[w14]
+mova z17.q, p2/m, za1v.q[w14, 0]
+// CHECK-INST: mov z17.q, p2/m, za1v.q[w14, 0]
// CHECK-ENCODING: [0x31,0xc8,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 c8 c3 c0 <unknown>
-mova z29.q, p2/m, za6v.q[w12]
-// CHECK-INST: mov z29.q, p2/m, za6v.q[w12]
+mova z29.q, p2/m, za6v.q[w12, 0]
+// CHECK-INST: mov z29.q, p2/m, za6v.q[w12, 0]
// CHECK-ENCODING: [0xdd,0x88,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 88 c3 c0 <unknown>
-mova z2.q, p5/m, za9v.q[w15]
-// CHECK-INST: mov z2.q, p5/m, za9v.q[w15]
+mova z2.q, p5/m, za9v.q[w15, 0]
+// CHECK-INST: mov z2.q, p5/m, za9v.q[w15, 0]
// CHECK-ENCODING: [0x22,0xf5,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 c3 c0 <unknown>
-mova z7.q, p2/m, za12v.q[w13]
-// CHECK-INST: mov z7.q, p2/m, za12v.q[w13]
+mova z7.q, p2/m, za12v.q[w13, 0]
+// CHECK-INST: mov z7.q, p2/m, za12v.q[w13, 0]
// CHECK-ENCODING: [0x87,0xa9,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 c3 c0 <unknown>
// Aliases
-mov z0.q, p0/m, za0v.q[w12]
-// CHECK-INST: mov z0.q, p0/m, za0v.q[w12]
+mov z0.q, p0/m, za0v.q[w12, 0]
+// CHECK-INST: mov z0.q, p0/m, za0v.q[w12, 0]
// CHECK-ENCODING: [0x00,0x80,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 c3 c0 <unknown>
-mov z21.q, p5/m, za10v.q[w14]
-// CHECK-INST: mov z21.q, p5/m, za10v.q[w14]
+mov z21.q, p5/m, za10v.q[w14, 0]
+// CHECK-INST: mov z21.q, p5/m, za10v.q[w14, 0]
// CHECK-ENCODING: [0x55,0xd5,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 55 d5 c3 c0 <unknown>
-mov z23.q, p3/m, za13v.q[w15]
-// CHECK-INST: mov z23.q, p3/m, za13v.q[w15]
+mov z23.q, p3/m, za13v.q[w15, 0]
+// CHECK-INST: mov z23.q, p3/m, za13v.q[w15, 0]
// CHECK-ENCODING: [0xb7,0xed,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: b7 ed c3 c0 <unknown>
-mov z31.q, p7/m, za15v.q[w15]
-// CHECK-INST: mov z31.q, p7/m, za15v.q[w15]
+mov z31.q, p7/m, za15v.q[w15, 0]
+// CHECK-INST: mov z31.q, p7/m, za15v.q[w15, 0]
// CHECK-ENCODING: [0xff,0xfd,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ff fd c3 c0 <unknown>
-mov z5.q, p3/m, za1v.q[w12]
-// CHECK-INST: mov z5.q, p3/m, za1v.q[w12]
+mov z5.q, p3/m, za1v.q[w12, 0]
+// CHECK-INST: mov z5.q, p3/m, za1v.q[w12, 0]
// CHECK-ENCODING: [0x25,0x8c,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8c c3 c0 <unknown>
-mov z1.q, p1/m, za1v.q[w12]
-// CHECK-INST: mov z1.q, p1/m, za1v.q[w12]
+mov z1.q, p1/m, za1v.q[w12, 0]
+// CHECK-INST: mov z1.q, p1/m, za1v.q[w12, 0]
// CHECK-ENCODING: [0x21,0x84,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 c3 c0 <unknown>
-mov z24.q, p5/m, za3v.q[w14]
-// CHECK-INST: mov z24.q, p5/m, za3v.q[w14]
+mov z24.q, p5/m, za3v.q[w14, 0]
+// CHECK-INST: mov z24.q, p5/m, za3v.q[w14, 0]
// CHECK-ENCODING: [0x78,0xd4,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 78 d4 c3 c0 <unknown>
-mov z0.q, p6/m, za12v.q[w12]
-// CHECK-INST: mov z0.q, p6/m, za12v.q[w12]
+mov z0.q, p6/m, za12v.q[w12, 0]
+// CHECK-INST: mov z0.q, p6/m, za12v.q[w12, 0]
// CHECK-ENCODING: [0x80,0x99,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 c3 c0 <unknown>
-mov z17.q, p2/m, za1v.q[w14]
-// CHECK-INST: mov z17.q, p2/m, za1v.q[w14]
+mov z17.q, p2/m, za1v.q[w14, 0]
+// CHECK-INST: mov z17.q, p2/m, za1v.q[w14, 0]
// CHECK-ENCODING: [0x31,0xc8,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 31 c8 c3 c0 <unknown>
-mov z29.q, p2/m, za6v.q[w12]
-// CHECK-INST: mov z29.q, p2/m, za6v.q[w12]
+mov z29.q, p2/m, za6v.q[w12, 0]
+// CHECK-INST: mov z29.q, p2/m, za6v.q[w12, 0]
// CHECK-ENCODING: [0xdd,0x88,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: dd 88 c3 c0 <unknown>
-mov z2.q, p5/m, za9v.q[w15]
-// CHECK-INST: mov z2.q, p5/m, za9v.q[w15]
+mov z2.q, p5/m, za9v.q[w15, 0]
+// CHECK-INST: mov z2.q, p5/m, za9v.q[w15, 0]
// CHECK-ENCODING: [0x22,0xf5,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 c3 c0 <unknown>
-mov z7.q, p2/m, za12v.q[w13]
-// CHECK-INST: mov z7.q, p2/m, za12v.q[w13]
+mov z7.q, p2/m, za12v.q[w13, 0]
+// CHECK-INST: mov z7.q, p2/m, za12v.q[w13, 0]
// CHECK-ENCODING: [0x87,0xa9,0xc3,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 c3 c0 <unknown>
@@ -1505,148 +1505,148 @@ mov z7.q, p2/m, za12v.q[w13]
// --------------------------------------------------------------------------//
// Insert, vector to tile, horizontal, 8-bit
-mova za0h.b[w12, #0], p0/m, z0.b
-// CHECK-INST: mov za0h.b[w12, #0], p0/m, z0.b
+mova za0h.b[w12, 0], p0/m, z0.b
+// CHECK-INST: mov za0h.b[w12, 0], p0/m, z0.b
// CHECK-ENCODING: [0x00,0x00,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 00 c0 <unknown>
-mova za0h.b[w14, #5], p5/m, z10.b
-// CHECK-INST: mov za0h.b[w14, #5], p5/m, z10.b
+mova za0h.b[w14, 5], p5/m, z10.b
+// CHECK-INST: mov za0h.b[w14, 5], p5/m, z10.b
// CHECK-ENCODING: [0x45,0x55,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 00 c0 <unknown>
-mova za0h.b[w15, #7], p3/m, z13.b
-// CHECK-INST: mov za0h.b[w15, #7], p3/m, z13.b
+mova za0h.b[w15, 7], p3/m, z13.b
+// CHECK-INST: mov za0h.b[w15, 7], p3/m, z13.b
// CHECK-ENCODING: [0xa7,0x6d,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 00 c0 <unknown>
-mova za0h.b[w15, #15], p7/m, z31.b
-// CHECK-INST: mov za0h.b[w15, #15], p7/m, z31.b
+mova za0h.b[w15, 15], p7/m, z31.b
+// CHECK-INST: mov za0h.b[w15, 15], p7/m, z31.b
// CHECK-ENCODING: [0xef,0x7f,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 00 c0 <unknown>
-mova za0h.b[w12, #5], p3/m, z17.b
-// CHECK-INST: mov za0h.b[w12, #5], p3/m, z17.b
+mova za0h.b[w12, 5], p3/m, z17.b
+// CHECK-INST: mov za0h.b[w12, 5], p3/m, z17.b
// CHECK-ENCODING: [0x25,0x0e,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 00 c0 <unknown>
-mova za0h.b[w12, #1], p1/m, z1.b
-// CHECK-INST: mov za0h.b[w12, #1], p1/m, z1.b
+mova za0h.b[w12, 1], p1/m, z1.b
+// CHECK-INST: mov za0h.b[w12, 1], p1/m, z1.b
// CHECK-ENCODING: [0x21,0x04,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 00 c0 <unknown>
-mova za0h.b[w14, #8], p5/m, z19.b
-// CHECK-INST: mov za0h.b[w14, #8], p5/m, z19.b
+mova za0h.b[w14, 8], p5/m, z19.b
+// CHECK-INST: mov za0h.b[w14, 8], p5/m, z19.b
// CHECK-ENCODING: [0x68,0x56,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 00 c0 <unknown>
-mova za0h.b[w12, #0], p6/m, z12.b
-// CHECK-INST: mov za0h.b[w12, #0], p6/m, z12.b
+mova za0h.b[w12, 0], p6/m, z12.b
+// CHECK-INST: mov za0h.b[w12, 0], p6/m, z12.b
// CHECK-ENCODING: [0x80,0x19,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 00 c0 <unknown>
-mova za0h.b[w14, #1], p2/m, z1.b
-// CHECK-INST: mov za0h.b[w14, #1], p2/m, z1.b
+mova za0h.b[w14, 1], p2/m, z1.b
+// CHECK-INST: mov za0h.b[w14, 1], p2/m, z1.b
// CHECK-ENCODING: [0x21,0x48,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 00 c0 <unknown>
-mova za0h.b[w12, #13], p2/m, z22.b
-// CHECK-INST: mov za0h.b[w12, #13], p2/m, z22.b
+mova za0h.b[w12, 13], p2/m, z22.b
+// CHECK-INST: mov za0h.b[w12, 13], p2/m, z22.b
// CHECK-ENCODING: [0xcd,0x0a,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 00 c0 <unknown>
-mova za0h.b[w15, #2], p5/m, z9.b
-// CHECK-INST: mov za0h.b[w15, #2], p5/m, z9.b
+mova za0h.b[w15, 2], p5/m, z9.b
+// CHECK-INST: mov za0h.b[w15, 2], p5/m, z9.b
// CHECK-ENCODING: [0x22,0x75,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 00 c0 <unknown>
-mova za0h.b[w13, #7], p2/m, z12.b
-// CHECK-INST: mov za0h.b[w13, #7], p2/m, z12.b
+mova za0h.b[w13, 7], p2/m, z12.b
+// CHECK-INST: mov za0h.b[w13, 7], p2/m, z12.b
// CHECK-ENCODING: [0x87,0x29,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 00 c0 <unknown>
// Aliases
-mov za0h.b[w12, #0], p0/m, z0.b
-// CHECK-INST: mov za0h.b[w12, #0], p0/m, z0.b
+mov za0h.b[w12, 0], p0/m, z0.b
+// CHECK-INST: mov za0h.b[w12, 0], p0/m, z0.b
// CHECK-ENCODING: [0x00,0x00,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 00 c0 <unknown>
-mov za0h.b[w14, #5], p5/m, z10.b
-// CHECK-INST: mov za0h.b[w14, #5], p5/m, z10.b
+mov za0h.b[w14, 5], p5/m, z10.b
+// CHECK-INST: mov za0h.b[w14, 5], p5/m, z10.b
// CHECK-ENCODING: [0x45,0x55,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 00 c0 <unknown>
-mov za0h.b[w15, #7], p3/m, z13.b
-// CHECK-INST: mov za0h.b[w15, #7], p3/m, z13.b
+mov za0h.b[w15, 7], p3/m, z13.b
+// CHECK-INST: mov za0h.b[w15, 7], p3/m, z13.b
// CHECK-ENCODING: [0xa7,0x6d,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 00 c0 <unknown>
-mov za0h.b[w15, #15], p7/m, z31.b
-// CHECK-INST: mov za0h.b[w15, #15], p7/m, z31.b
+mov za0h.b[w15, 15], p7/m, z31.b
+// CHECK-INST: mov za0h.b[w15, 15], p7/m, z31.b
// CHECK-ENCODING: [0xef,0x7f,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 00 c0 <unknown>
-mov za0h.b[w12, #5], p3/m, z17.b
-// CHECK-INST: mov za0h.b[w12, #5], p3/m, z17.b
+mov za0h.b[w12, 5], p3/m, z17.b
+// CHECK-INST: mov za0h.b[w12, 5], p3/m, z17.b
// CHECK-ENCODING: [0x25,0x0e,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 00 c0 <unknown>
-mov za0h.b[w12, #1], p1/m, z1.b
-// CHECK-INST: mov za0h.b[w12, #1], p1/m, z1.b
+mov za0h.b[w12, 1], p1/m, z1.b
+// CHECK-INST: mov za0h.b[w12, 1], p1/m, z1.b
// CHECK-ENCODING: [0x21,0x04,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 00 c0 <unknown>
-mov za0h.b[w14, #8], p5/m, z19.b
-// CHECK-INST: mov za0h.b[w14, #8], p5/m, z19.b
+mov za0h.b[w14, 8], p5/m, z19.b
+// CHECK-INST: mov za0h.b[w14, 8], p5/m, z19.b
// CHECK-ENCODING: [0x68,0x56,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 00 c0 <unknown>
-mov za0h.b[w12, #0], p6/m, z12.b
-// CHECK-INST: mov za0h.b[w12, #0], p6/m, z12.b
+mov za0h.b[w12, 0], p6/m, z12.b
+// CHECK-INST: mov za0h.b[w12, 0], p6/m, z12.b
// CHECK-ENCODING: [0x80,0x19,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 00 c0 <unknown>
-mov za0h.b[w14, #1], p2/m, z1.b
-// CHECK-INST: mov za0h.b[w14, #1], p2/m, z1.b
+mov za0h.b[w14, 1], p2/m, z1.b
+// CHECK-INST: mov za0h.b[w14, 1], p2/m, z1.b
// CHECK-ENCODING: [0x21,0x48,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 00 c0 <unknown>
-mov za0h.b[w12, #13], p2/m, z22.b
-// CHECK-INST: mov za0h.b[w12, #13], p2/m, z22.b
+mov za0h.b[w12, 13], p2/m, z22.b
+// CHECK-INST: mov za0h.b[w12, 13], p2/m, z22.b
// CHECK-ENCODING: [0xcd,0x0a,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 00 c0 <unknown>
-mov za0h.b[w15, #2], p5/m, z9.b
-// CHECK-INST: mov za0h.b[w15, #2], p5/m, z9.b
+mov za0h.b[w15, 2], p5/m, z9.b
+// CHECK-INST: mov za0h.b[w15, 2], p5/m, z9.b
// CHECK-ENCODING: [0x22,0x75,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 00 c0 <unknown>
-mov za0h.b[w13, #7], p2/m, z12.b
-// CHECK-INST: mov za0h.b[w13, #7], p2/m, z12.b
+mov za0h.b[w13, 7], p2/m, z12.b
+// CHECK-INST: mov za0h.b[w13, 7], p2/m, z12.b
// CHECK-ENCODING: [0x87,0x29,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 00 c0 <unknown>
@@ -1654,148 +1654,148 @@ mov za0h.b[w13, #7], p2/m, z12.b
// --------------------------------------------------------------------------//
// Insert, vector to tile, vertical, 8-bit
-mova za0v.b[w12, #0], p0/m, z0.b
-// CHECK-INST: mov za0v.b[w12, #0], p0/m, z0.b
+mova za0v.b[w12, 0], p0/m, z0.b
+// CHECK-INST: mov za0v.b[w12, 0], p0/m, z0.b
// CHECK-ENCODING: [0x00,0x80,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 00 c0 <unknown>
-mova za0v.b[w14, #5], p5/m, z10.b
-// CHECK-INST: mov za0v.b[w14, #5], p5/m, z10.b
+mova za0v.b[w14, 5], p5/m, z10.b
+// CHECK-INST: mov za0v.b[w14, 5], p5/m, z10.b
// CHECK-ENCODING: [0x45,0xd5,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 00 c0 <unknown>
-mova za0v.b[w15, #7], p3/m, z13.b
-// CHECK-INST: mov za0v.b[w15, #7], p3/m, z13.b
+mova za0v.b[w15, 7], p3/m, z13.b
+// CHECK-INST: mov za0v.b[w15, 7], p3/m, z13.b
// CHECK-ENCODING: [0xa7,0xed,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 00 c0 <unknown>
-mova za0v.b[w15, #15], p7/m, z31.b
-// CHECK-INST: mov za0v.b[w15, #15], p7/m, z31.b
+mova za0v.b[w15, 15], p7/m, z31.b
+// CHECK-INST: mov za0v.b[w15, 15], p7/m, z31.b
// CHECK-ENCODING: [0xef,0xff,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 00 c0 <unknown>
-mova za0v.b[w12, #5], p3/m, z17.b
-// CHECK-INST: mov za0v.b[w12, #5], p3/m, z17.b
+mova za0v.b[w12, 5], p3/m, z17.b
+// CHECK-INST: mov za0v.b[w12, 5], p3/m, z17.b
// CHECK-ENCODING: [0x25,0x8e,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 00 c0 <unknown>
-mova za0v.b[w12, #1], p1/m, z1.b
-// CHECK-INST: mov za0v.b[w12, #1], p1/m, z1.b
+mova za0v.b[w12, 1], p1/m, z1.b
+// CHECK-INST: mov za0v.b[w12, 1], p1/m, z1.b
// CHECK-ENCODING: [0x21,0x84,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 00 c0 <unknown>
-mova za0v.b[w14, #8], p5/m, z19.b
-// CHECK-INST: mov za0v.b[w14, #8], p5/m, z19.b
+mova za0v.b[w14, 8], p5/m, z19.b
+// CHECK-INST: mov za0v.b[w14, 8], p5/m, z19.b
// CHECK-ENCODING: [0x68,0xd6,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 00 c0 <unknown>
-mova za0v.b[w12, #0], p6/m, z12.b
-// CHECK-INST: mov za0v.b[w12, #0], p6/m, z12.b
+mova za0v.b[w12, 0], p6/m, z12.b
+// CHECK-INST: mov za0v.b[w12, 0], p6/m, z12.b
// CHECK-ENCODING: [0x80,0x99,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 00 c0 <unknown>
-mova za0v.b[w14, #1], p2/m, z1.b
-// CHECK-INST: mov za0v.b[w14, #1], p2/m, z1.b
+mova za0v.b[w14, 1], p2/m, z1.b
+// CHECK-INST: mov za0v.b[w14, 1], p2/m, z1.b
// CHECK-ENCODING: [0x21,0xc8,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 00 c0 <unknown>
-mova za0v.b[w12, #13], p2/m, z22.b
-// CHECK-INST: mov za0v.b[w12, #13], p2/m, z22.b
+mova za0v.b[w12, 13], p2/m, z22.b
+// CHECK-INST: mov za0v.b[w12, 13], p2/m, z22.b
// CHECK-ENCODING: [0xcd,0x8a,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 00 c0 <unknown>
-mova za0v.b[w15, #2], p5/m, z9.b
-// CHECK-INST: mov za0v.b[w15, #2], p5/m, z9.b
+mova za0v.b[w15, 2], p5/m, z9.b
+// CHECK-INST: mov za0v.b[w15, 2], p5/m, z9.b
// CHECK-ENCODING: [0x22,0xf5,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 00 c0 <unknown>
-mova za0v.b[w13, #7], p2/m, z12.b
-// CHECK-INST: mov za0v.b[w13, #7], p2/m, z12.b
+mova za0v.b[w13, 7], p2/m, z12.b
+// CHECK-INST: mov za0v.b[w13, 7], p2/m, z12.b
// CHECK-ENCODING: [0x87,0xa9,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 00 c0 <unknown>
// Aliases
-mov za0v.b[w12, #0], p0/m, z0.b
-// CHECK-INST: mov za0v.b[w12, #0], p0/m, z0.b
+mov za0v.b[w12, 0], p0/m, z0.b
+// CHECK-INST: mov za0v.b[w12, 0], p0/m, z0.b
// CHECK-ENCODING: [0x00,0x80,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 00 c0 <unknown>
-mov za0v.b[w14, #5], p5/m, z10.b
-// CHECK-INST: mov za0v.b[w14, #5], p5/m, z10.b
+mov za0v.b[w14, 5], p5/m, z10.b
+// CHECK-INST: mov za0v.b[w14, 5], p5/m, z10.b
// CHECK-ENCODING: [0x45,0xd5,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 00 c0 <unknown>
-mov za0v.b[w15, #7], p3/m, z13.b
-// CHECK-INST: mov za0v.b[w15, #7], p3/m, z13.b
+mov za0v.b[w15, 7], p3/m, z13.b
+// CHECK-INST: mov za0v.b[w15, 7], p3/m, z13.b
// CHECK-ENCODING: [0xa7,0xed,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 00 c0 <unknown>
-mov za0v.b[w15, #15], p7/m, z31.b
-// CHECK-INST: mov za0v.b[w15, #15], p7/m, z31.b
+mov za0v.b[w15, 15], p7/m, z31.b
+// CHECK-INST: mov za0v.b[w15, 15], p7/m, z31.b
// CHECK-ENCODING: [0xef,0xff,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 00 c0 <unknown>
-mov za0v.b[w12, #5], p3/m, z17.b
-// CHECK-INST: mov za0v.b[w12, #5], p3/m, z17.b
+mov za0v.b[w12, 5], p3/m, z17.b
+// CHECK-INST: mov za0v.b[w12, 5], p3/m, z17.b
// CHECK-ENCODING: [0x25,0x8e,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 00 c0 <unknown>
-mov za0v.b[w12, #1], p1/m, z1.b
-// CHECK-INST: mov za0v.b[w12, #1], p1/m, z1.b
+mov za0v.b[w12, 1], p1/m, z1.b
+// CHECK-INST: mov za0v.b[w12, 1], p1/m, z1.b
// CHECK-ENCODING: [0x21,0x84,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 00 c0 <unknown>
-mov za0v.b[w14, #8], p5/m, z19.b
-// CHECK-INST: mov za0v.b[w14, #8], p5/m, z19.b
+mov za0v.b[w14, 8], p5/m, z19.b
+// CHECK-INST: mov za0v.b[w14, 8], p5/m, z19.b
// CHECK-ENCODING: [0x68,0xd6,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 00 c0 <unknown>
-mov za0v.b[w12, #0], p6/m, z12.b
-// CHECK-INST: mov za0v.b[w12, #0], p6/m, z12.b
+mov za0v.b[w12, 0], p6/m, z12.b
+// CHECK-INST: mov za0v.b[w12, 0], p6/m, z12.b
// CHECK-ENCODING: [0x80,0x99,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 00 c0 <unknown>
-mov za0v.b[w14, #1], p2/m, z1.b
-// CHECK-INST: mov za0v.b[w14, #1], p2/m, z1.b
+mov za0v.b[w14, 1], p2/m, z1.b
+// CHECK-INST: mov za0v.b[w14, 1], p2/m, z1.b
// CHECK-ENCODING: [0x21,0xc8,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 00 c0 <unknown>
-mov za0v.b[w12, #13], p2/m, z22.b
-// CHECK-INST: mov za0v.b[w12, #13], p2/m, z22.b
+mov za0v.b[w12, 13], p2/m, z22.b
+// CHECK-INST: mov za0v.b[w12, 13], p2/m, z22.b
// CHECK-ENCODING: [0xcd,0x8a,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 00 c0 <unknown>
-mov za0v.b[w15, #2], p5/m, z9.b
-// CHECK-INST: mov za0v.b[w15, #2], p5/m, z9.b
+mov za0v.b[w15, 2], p5/m, z9.b
+// CHECK-INST: mov za0v.b[w15, 2], p5/m, z9.b
// CHECK-ENCODING: [0x22,0xf5,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 00 c0 <unknown>
-mov za0v.b[w13, #7], p2/m, z12.b
-// CHECK-INST: mov za0v.b[w13, #7], p2/m, z12.b
+mov za0v.b[w13, 7], p2/m, z12.b
+// CHECK-INST: mov za0v.b[w13, 7], p2/m, z12.b
// CHECK-ENCODING: [0x87,0xa9,0x00,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 00 c0 <unknown>
@@ -1803,148 +1803,148 @@ mov za0v.b[w13, #7], p2/m, z12.b
// --------------------------------------------------------------------------//
// Insert, vector to tile, horizontal, 16-bit
-mova za0h.h[w12, #0], p0/m, z0.h
-// CHECK-INST: mov za0h.h[w12, #0], p0/m, z0.h
+mova za0h.h[w12, 0], p0/m, z0.h
+// CHECK-INST: mov za0h.h[w12, 0], p0/m, z0.h
// CHECK-ENCODING: [0x00,0x00,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 40 c0 <unknown>
-mova za0h.h[w14, #5], p5/m, z10.h
-// CHECK-INST: mov za0h.h[w14, #5], p5/m, z10.h
+mova za0h.h[w14, 5], p5/m, z10.h
+// CHECK-INST: mov za0h.h[w14, 5], p5/m, z10.h
// CHECK-ENCODING: [0x45,0x55,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 40 c0 <unknown>
-mova za0h.h[w15, #7], p3/m, z13.h
-// CHECK-INST: mov za0h.h[w15, #7], p3/m, z13.h
+mova za0h.h[w15, 7], p3/m, z13.h
+// CHECK-INST: mov za0h.h[w15, 7], p3/m, z13.h
// CHECK-ENCODING: [0xa7,0x6d,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 40 c0 <unknown>
-mova za1h.h[w15, #7], p7/m, z31.h
-// CHECK-INST: mov za1h.h[w15, #7], p7/m, z31.h
+mova za1h.h[w15, 7], p7/m, z31.h
+// CHECK-INST: mov za1h.h[w15, 7], p7/m, z31.h
// CHECK-ENCODING: [0xef,0x7f,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 40 c0 <unknown>
-mova za0h.h[w12, #5], p3/m, z17.h
-// CHECK-INST: mov za0h.h[w12, #5], p3/m, z17.h
+mova za0h.h[w12, 5], p3/m, z17.h
+// CHECK-INST: mov za0h.h[w12, 5], p3/m, z17.h
// CHECK-ENCODING: [0x25,0x0e,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 40 c0 <unknown>
-mova za0h.h[w12, #1], p1/m, z1.h
-// CHECK-INST: mov za0h.h[w12, #1], p1/m, z1.h
+mova za0h.h[w12, 1], p1/m, z1.h
+// CHECK-INST: mov za0h.h[w12, 1], p1/m, z1.h
// CHECK-ENCODING: [0x21,0x04,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 40 c0 <unknown>
-mova za1h.h[w14, #0], p5/m, z19.h
-// CHECK-INST: mov za1h.h[w14, #0], p5/m, z19.h
+mova za1h.h[w14, 0], p5/m, z19.h
+// CHECK-INST: mov za1h.h[w14, 0], p5/m, z19.h
// CHECK-ENCODING: [0x68,0x56,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 40 c0 <unknown>
-mova za0h.h[w12, #0], p6/m, z12.h
-// CHECK-INST: mov za0h.h[w12, #0], p6/m, z12.h
+mova za0h.h[w12, 0], p6/m, z12.h
+// CHECK-INST: mov za0h.h[w12, 0], p6/m, z12.h
// CHECK-ENCODING: [0x80,0x19,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 40 c0 <unknown>
-mova za0h.h[w14, #1], p2/m, z1.h
-// CHECK-INST: mov za0h.h[w14, #1], p2/m, z1.h
+mova za0h.h[w14, 1], p2/m, z1.h
+// CHECK-INST: mov za0h.h[w14, 1], p2/m, z1.h
// CHECK-ENCODING: [0x21,0x48,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 40 c0 <unknown>
-mova za1h.h[w12, #5], p2/m, z22.h
-// CHECK-INST: mov za1h.h[w12, #5], p2/m, z22.h
+mova za1h.h[w12, 5], p2/m, z22.h
+// CHECK-INST: mov za1h.h[w12, 5], p2/m, z22.h
// CHECK-ENCODING: [0xcd,0x0a,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 40 c0 <unknown>
-mova za0h.h[w15, #2], p5/m, z9.h
-// CHECK-INST: mov za0h.h[w15, #2], p5/m, z9.h
+mova za0h.h[w15, 2], p5/m, z9.h
+// CHECK-INST: mov za0h.h[w15, 2], p5/m, z9.h
// CHECK-ENCODING: [0x22,0x75,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 40 c0 <unknown>
-mova za0h.h[w13, #7], p2/m, z12.h
-// CHECK-INST: mov za0h.h[w13, #7], p2/m, z12.h
+mova za0h.h[w13, 7], p2/m, z12.h
+// CHECK-INST: mov za0h.h[w13, 7], p2/m, z12.h
// CHECK-ENCODING: [0x87,0x29,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 40 c0 <unknown>
// Aliases
-mov za0h.h[w12, #0], p0/m, z0.h
-// CHECK-INST: mov za0h.h[w12, #0], p0/m, z0.h
+mov za0h.h[w12, 0], p0/m, z0.h
+// CHECK-INST: mov za0h.h[w12, 0], p0/m, z0.h
// CHECK-ENCODING: [0x00,0x00,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 40 c0 <unknown>
-mov za0h.h[w14, #5], p5/m, z10.h
-// CHECK-INST: mov za0h.h[w14, #5], p5/m, z10.h
+mov za0h.h[w14, 5], p5/m, z10.h
+// CHECK-INST: mov za0h.h[w14, 5], p5/m, z10.h
// CHECK-ENCODING: [0x45,0x55,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 40 c0 <unknown>
-mov za0h.h[w15, #7], p3/m, z13.h
-// CHECK-INST: mov za0h.h[w15, #7], p3/m, z13.h
+mov za0h.h[w15, 7], p3/m, z13.h
+// CHECK-INST: mov za0h.h[w15, 7], p3/m, z13.h
// CHECK-ENCODING: [0xa7,0x6d,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 40 c0 <unknown>
-mov za1h.h[w15, #7], p7/m, z31.h
-// CHECK-INST: mov za1h.h[w15, #7], p7/m, z31.h
+mov za1h.h[w15, 7], p7/m, z31.h
+// CHECK-INST: mov za1h.h[w15, 7], p7/m, z31.h
// CHECK-ENCODING: [0xef,0x7f,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 40 c0 <unknown>
-mov za0h.h[w12, #5], p3/m, z17.h
-// CHECK-INST: mov za0h.h[w12, #5], p3/m, z17.h
+mov za0h.h[w12, 5], p3/m, z17.h
+// CHECK-INST: mov za0h.h[w12, 5], p3/m, z17.h
// CHECK-ENCODING: [0x25,0x0e,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 40 c0 <unknown>
-mov za0h.h[w12, #1], p1/m, z1.h
-// CHECK-INST: mov za0h.h[w12, #1], p1/m, z1.h
+mov za0h.h[w12, 1], p1/m, z1.h
+// CHECK-INST: mov za0h.h[w12, 1], p1/m, z1.h
// CHECK-ENCODING: [0x21,0x04,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 40 c0 <unknown>
-mov za1h.h[w14, #0], p5/m, z19.h
-// CHECK-INST: mov za1h.h[w14, #0], p5/m, z19.h
+mov za1h.h[w14, 0], p5/m, z19.h
+// CHECK-INST: mov za1h.h[w14, 0], p5/m, z19.h
// CHECK-ENCODING: [0x68,0x56,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 40 c0 <unknown>
-mov za0h.h[w12, #0], p6/m, z12.h
-// CHECK-INST: mov za0h.h[w12, #0], p6/m, z12.h
+mov za0h.h[w12, 0], p6/m, z12.h
+// CHECK-INST: mov za0h.h[w12, 0], p6/m, z12.h
// CHECK-ENCODING: [0x80,0x19,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 40 c0 <unknown>
-mov za0h.h[w14, #1], p2/m, z1.h
-// CHECK-INST: mov za0h.h[w14, #1], p2/m, z1.h
+mov za0h.h[w14, 1], p2/m, z1.h
+// CHECK-INST: mov za0h.h[w14, 1], p2/m, z1.h
// CHECK-ENCODING: [0x21,0x48,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 40 c0 <unknown>
-mov za1h.h[w12, #5], p2/m, z22.h
-// CHECK-INST: mov za1h.h[w12, #5], p2/m, z22.h
+mov za1h.h[w12, 5], p2/m, z22.h
+// CHECK-INST: mov za1h.h[w12, 5], p2/m, z22.h
// CHECK-ENCODING: [0xcd,0x0a,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 40 c0 <unknown>
-mov za0h.h[w15, #2], p5/m, z9.h
-// CHECK-INST: mov za0h.h[w15, #2], p5/m, z9.h
+mov za0h.h[w15, 2], p5/m, z9.h
+// CHECK-INST: mov za0h.h[w15, 2], p5/m, z9.h
// CHECK-ENCODING: [0x22,0x75,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 40 c0 <unknown>
-mov za0h.h[w13, #7], p2/m, z12.h
-// CHECK-INST: mov za0h.h[w13, #7], p2/m, z12.h
+mov za0h.h[w13, 7], p2/m, z12.h
+// CHECK-INST: mov za0h.h[w13, 7], p2/m, z12.h
// CHECK-ENCODING: [0x87,0x29,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 40 c0 <unknown>
@@ -1952,148 +1952,148 @@ mov za0h.h[w13, #7], p2/m, z12.h
// --------------------------------------------------------------------------//
// Insert, vector to tile, vertical, 16-bit
-mova za0v.h[w12, #0], p0/m, z0.h
-// CHECK-INST: mov za0v.h[w12, #0], p0/m, z0.h
+mova za0v.h[w12, 0], p0/m, z0.h
+// CHECK-INST: mov za0v.h[w12, 0], p0/m, z0.h
// CHECK-ENCODING: [0x00,0x80,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 40 c0 <unknown>
-mova za0v.h[w14, #5], p5/m, z10.h
-// CHECK-INST: mov za0v.h[w14, #5], p5/m, z10.h
+mova za0v.h[w14, 5], p5/m, z10.h
+// CHECK-INST: mov za0v.h[w14, 5], p5/m, z10.h
// CHECK-ENCODING: [0x45,0xd5,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 40 c0 <unknown>
-mova za0v.h[w15, #7], p3/m, z13.h
-// CHECK-INST: mov za0v.h[w15, #7], p3/m, z13.h
+mova za0v.h[w15, 7], p3/m, z13.h
+// CHECK-INST: mov za0v.h[w15, 7], p3/m, z13.h
// CHECK-ENCODING: [0xa7,0xed,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 40 c0 <unknown>
-mova za1v.h[w15, #7], p7/m, z31.h
-// CHECK-INST: mov za1v.h[w15, #7], p7/m, z31.h
+mova za1v.h[w15, 7], p7/m, z31.h
+// CHECK-INST: mov za1v.h[w15, 7], p7/m, z31.h
// CHECK-ENCODING: [0xef,0xff,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 40 c0 <unknown>
-mova za0v.h[w12, #5], p3/m, z17.h
-// CHECK-INST: mov za0v.h[w12, #5], p3/m, z17.h
+mova za0v.h[w12, 5], p3/m, z17.h
+// CHECK-INST: mov za0v.h[w12, 5], p3/m, z17.h
// CHECK-ENCODING: [0x25,0x8e,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 40 c0 <unknown>
-mova za0v.h[w12, #1], p1/m, z1.h
-// CHECK-INST: mov za0v.h[w12, #1], p1/m, z1.h
+mova za0v.h[w12, 1], p1/m, z1.h
+// CHECK-INST: mov za0v.h[w12, 1], p1/m, z1.h
// CHECK-ENCODING: [0x21,0x84,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 40 c0 <unknown>
-mova za1v.h[w14, #0], p5/m, z19.h
-// CHECK-INST: mov za1v.h[w14, #0], p5/m, z19.h
+mova za1v.h[w14, 0], p5/m, z19.h
+// CHECK-INST: mov za1v.h[w14, 0], p5/m, z19.h
// CHECK-ENCODING: [0x68,0xd6,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 40 c0 <unknown>
-mova za0v.h[w12, #0], p6/m, z12.h
-// CHECK-INST: mov za0v.h[w12, #0], p6/m, z12.h
+mova za0v.h[w12, 0], p6/m, z12.h
+// CHECK-INST: mov za0v.h[w12, 0], p6/m, z12.h
// CHECK-ENCODING: [0x80,0x99,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 40 c0 <unknown>
-mova za0v.h[w14, #1], p2/m, z1.h
-// CHECK-INST: mov za0v.h[w14, #1], p2/m, z1.h
+mova za0v.h[w14, 1], p2/m, z1.h
+// CHECK-INST: mov za0v.h[w14, 1], p2/m, z1.h
// CHECK-ENCODING: [0x21,0xc8,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 40 c0 <unknown>
-mova za1v.h[w12, #5], p2/m, z22.h
-// CHECK-INST: mov za1v.h[w12, #5], p2/m, z22.h
+mova za1v.h[w12, 5], p2/m, z22.h
+// CHECK-INST: mov za1v.h[w12, 5], p2/m, z22.h
// CHECK-ENCODING: [0xcd,0x8a,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 40 c0 <unknown>
-mova za0v.h[w15, #2], p5/m, z9.h
-// CHECK-INST: mov za0v.h[w15, #2], p5/m, z9.h
+mova za0v.h[w15, 2], p5/m, z9.h
+// CHECK-INST: mov za0v.h[w15, 2], p5/m, z9.h
// CHECK-ENCODING: [0x22,0xf5,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 40 c0 <unknown>
-mova za0v.h[w13, #7], p2/m, z12.h
-// CHECK-INST: mov za0v.h[w13, #7], p2/m, z12.h
+mova za0v.h[w13, 7], p2/m, z12.h
+// CHECK-INST: mov za0v.h[w13, 7], p2/m, z12.h
// CHECK-ENCODING: [0x87,0xa9,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 40 c0 <unknown>
// Aliases
-mov za0v.h[w12, #0], p0/m, z0.h
-// CHECK-INST: mov za0v.h[w12, #0], p0/m, z0.h
+mov za0v.h[w12, 0], p0/m, z0.h
+// CHECK-INST: mov za0v.h[w12, 0], p0/m, z0.h
// CHECK-ENCODING: [0x00,0x80,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 40 c0 <unknown>
-mov za0v.h[w14, #5], p5/m, z10.h
-// CHECK-INST: mov za0v.h[w14, #5], p5/m, z10.h
+mov za0v.h[w14, 5], p5/m, z10.h
+// CHECK-INST: mov za0v.h[w14, 5], p5/m, z10.h
// CHECK-ENCODING: [0x45,0xd5,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 40 c0 <unknown>
-mov za0v.h[w15, #7], p3/m, z13.h
-// CHECK-INST: mov za0v.h[w15, #7], p3/m, z13.h
+mov za0v.h[w15, 7], p3/m, z13.h
+// CHECK-INST: mov za0v.h[w15, 7], p3/m, z13.h
// CHECK-ENCODING: [0xa7,0xed,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 40 c0 <unknown>
-mov za1v.h[w15, #7], p7/m, z31.h
-// CHECK-INST: mov za1v.h[w15, #7], p7/m, z31.h
+mov za1v.h[w15, 7], p7/m, z31.h
+// CHECK-INST: mov za1v.h[w15, 7], p7/m, z31.h
// CHECK-ENCODING: [0xef,0xff,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 40 c0 <unknown>
-mov za0v.h[w12, #5], p3/m, z17.h
-// CHECK-INST: mov za0v.h[w12, #5], p3/m, z17.h
+mov za0v.h[w12, 5], p3/m, z17.h
+// CHECK-INST: mov za0v.h[w12, 5], p3/m, z17.h
// CHECK-ENCODING: [0x25,0x8e,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 40 c0 <unknown>
-mov za0v.h[w12, #1], p1/m, z1.h
-// CHECK-INST: mov za0v.h[w12, #1], p1/m, z1.h
+mov za0v.h[w12, 1], p1/m, z1.h
+// CHECK-INST: mov za0v.h[w12, 1], p1/m, z1.h
// CHECK-ENCODING: [0x21,0x84,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 40 c0 <unknown>
-mov za1v.h[w14, #0], p5/m, z19.h
-// CHECK-INST: mov za1v.h[w14, #0], p5/m, z19.h
+mov za1v.h[w14, 0], p5/m, z19.h
+// CHECK-INST: mov za1v.h[w14, 0], p5/m, z19.h
// CHECK-ENCODING: [0x68,0xd6,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 40 c0 <unknown>
-mov za0v.h[w12, #0], p6/m, z12.h
-// CHECK-INST: mov za0v.h[w12, #0], p6/m, z12.h
+mov za0v.h[w12, 0], p6/m, z12.h
+// CHECK-INST: mov za0v.h[w12, 0], p6/m, z12.h
// CHECK-ENCODING: [0x80,0x99,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 40 c0 <unknown>
-mov za0v.h[w14, #1], p2/m, z1.h
-// CHECK-INST: mov za0v.h[w14, #1], p2/m, z1.h
+mov za0v.h[w14, 1], p2/m, z1.h
+// CHECK-INST: mov za0v.h[w14, 1], p2/m, z1.h
// CHECK-ENCODING: [0x21,0xc8,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 40 c0 <unknown>
-mov za1v.h[w12, #5], p2/m, z22.h
-// CHECK-INST: mov za1v.h[w12, #5], p2/m, z22.h
+mov za1v.h[w12, 5], p2/m, z22.h
+// CHECK-INST: mov za1v.h[w12, 5], p2/m, z22.h
// CHECK-ENCODING: [0xcd,0x8a,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 40 c0 <unknown>
-mov za0v.h[w15, #2], p5/m, z9.h
-// CHECK-INST: mov za0v.h[w15, #2], p5/m, z9.h
+mov za0v.h[w15, 2], p5/m, z9.h
+// CHECK-INST: mov za0v.h[w15, 2], p5/m, z9.h
// CHECK-ENCODING: [0x22,0xf5,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 40 c0 <unknown>
-mov za0v.h[w13, #7], p2/m, z12.h
-// CHECK-INST: mov za0v.h[w13, #7], p2/m, z12.h
+mov za0v.h[w13, 7], p2/m, z12.h
+// CHECK-INST: mov za0v.h[w13, 7], p2/m, z12.h
// CHECK-ENCODING: [0x87,0xa9,0x40,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 40 c0 <unknown>
@@ -2101,148 +2101,148 @@ mov za0v.h[w13, #7], p2/m, z12.h
// --------------------------------------------------------------------------//
// Insert, vector to tile, horizontal, 32-bit
-mova za0h.s[w12, #0], p0/m, z0.s
-// CHECK-INST: mov za0h.s[w12, #0], p0/m, z0.s
+mova za0h.s[w12, 0], p0/m, z0.s
+// CHECK-INST: mov za0h.s[w12, 0], p0/m, z0.s
// CHECK-ENCODING: [0x00,0x00,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 80 c0 <unknown>
-mova za1h.s[w14, #1], p5/m, z10.s
-// CHECK-INST: mov za1h.s[w14, #1], p5/m, z10.s
+mova za1h.s[w14, 1], p5/m, z10.s
+// CHECK-INST: mov za1h.s[w14, 1], p5/m, z10.s
// CHECK-ENCODING: [0x45,0x55,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 80 c0 <unknown>
-mova za1h.s[w15, #3], p3/m, z13.s
-// CHECK-INST: mov za1h.s[w15, #3], p3/m, z13.s
+mova za1h.s[w15, 3], p3/m, z13.s
+// CHECK-INST: mov za1h.s[w15, 3], p3/m, z13.s
// CHECK-ENCODING: [0xa7,0x6d,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 80 c0 <unknown>
-mova za3h.s[w15, #3], p7/m, z31.s
-// CHECK-INST: mov za3h.s[w15, #3], p7/m, z31.s
+mova za3h.s[w15, 3], p7/m, z31.s
+// CHECK-INST: mov za3h.s[w15, 3], p7/m, z31.s
// CHECK-ENCODING: [0xef,0x7f,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 80 c0 <unknown>
-mova za1h.s[w12, #1], p3/m, z17.s
-// CHECK-INST: mov za1h.s[w12, #1], p3/m, z17.s
+mova za1h.s[w12, 1], p3/m, z17.s
+// CHECK-INST: mov za1h.s[w12, 1], p3/m, z17.s
// CHECK-ENCODING: [0x25,0x0e,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 80 c0 <unknown>
-mova za0h.s[w12, #1], p1/m, z1.s
-// CHECK-INST: mov za0h.s[w12, #1], p1/m, z1.s
+mova za0h.s[w12, 1], p1/m, z1.s
+// CHECK-INST: mov za0h.s[w12, 1], p1/m, z1.s
// CHECK-ENCODING: [0x21,0x04,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 80 c0 <unknown>
-mova za2h.s[w14, #0], p5/m, z19.s
-// CHECK-INST: mov za2h.s[w14, #0], p5/m, z19.s
+mova za2h.s[w14, 0], p5/m, z19.s
+// CHECK-INST: mov za2h.s[w14, 0], p5/m, z19.s
// CHECK-ENCODING: [0x68,0x56,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 80 c0 <unknown>
-mova za0h.s[w12, #0], p6/m, z12.s
-// CHECK-INST: mov za0h.s[w12, #0], p6/m, z12.s
+mova za0h.s[w12, 0], p6/m, z12.s
+// CHECK-INST: mov za0h.s[w12, 0], p6/m, z12.s
// CHECK-ENCODING: [0x80,0x19,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 80 c0 <unknown>
-mova za0h.s[w14, #1], p2/m, z1.s
-// CHECK-INST: mov za0h.s[w14, #1], p2/m, z1.s
+mova za0h.s[w14, 1], p2/m, z1.s
+// CHECK-INST: mov za0h.s[w14, 1], p2/m, z1.s
// CHECK-ENCODING: [0x21,0x48,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 80 c0 <unknown>
-mova za3h.s[w12, #1], p2/m, z22.s
-// CHECK-INST: mov za3h.s[w12, #1], p2/m, z22.s
+mova za3h.s[w12, 1], p2/m, z22.s
+// CHECK-INST: mov za3h.s[w12, 1], p2/m, z22.s
// CHECK-ENCODING: [0xcd,0x0a,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 80 c0 <unknown>
-mova za0h.s[w15, #2], p5/m, z9.s
-// CHECK-INST: mov za0h.s[w15, #2], p5/m, z9.s
+mova za0h.s[w15, 2], p5/m, z9.s
+// CHECK-INST: mov za0h.s[w15, 2], p5/m, z9.s
// CHECK-ENCODING: [0x22,0x75,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 80 c0 <unknown>
-mova za1h.s[w13, #3], p2/m, z12.s
-// CHECK-INST: mov za1h.s[w13, #3], p2/m, z12.s
+mova za1h.s[w13, 3], p2/m, z12.s
+// CHECK-INST: mov za1h.s[w13, 3], p2/m, z12.s
// CHECK-ENCODING: [0x87,0x29,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 80 c0 <unknown>
// Aliases
-mov za0h.s[w12, #0], p0/m, z0.s
-// CHECK-INST: mov za0h.s[w12, #0], p0/m, z0.s
+mov za0h.s[w12, 0], p0/m, z0.s
+// CHECK-INST: mov za0h.s[w12, 0], p0/m, z0.s
// CHECK-ENCODING: [0x00,0x00,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 80 c0 <unknown>
-mov za1h.s[w14, #1], p5/m, z10.s
-// CHECK-INST: mov za1h.s[w14, #1], p5/m, z10.s
+mov za1h.s[w14, 1], p5/m, z10.s
+// CHECK-INST: mov za1h.s[w14, 1], p5/m, z10.s
// CHECK-ENCODING: [0x45,0x55,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 80 c0 <unknown>
-mov za1h.s[w15, #3], p3/m, z13.s
-// CHECK-INST: mov za1h.s[w15, #3], p3/m, z13.s
+mov za1h.s[w15, 3], p3/m, z13.s
+// CHECK-INST: mov za1h.s[w15, 3], p3/m, z13.s
// CHECK-ENCODING: [0xa7,0x6d,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 80 c0 <unknown>
-mov za3h.s[w15, #3], p7/m, z31.s
-// CHECK-INST: mov za3h.s[w15, #3], p7/m, z31.s
+mov za3h.s[w15, 3], p7/m, z31.s
+// CHECK-INST: mov za3h.s[w15, 3], p7/m, z31.s
// CHECK-ENCODING: [0xef,0x7f,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 80 c0 <unknown>
-mov za1h.s[w12, #1], p3/m, z17.s
-// CHECK-INST: mov za1h.s[w12, #1], p3/m, z17.s
+mov za1h.s[w12, 1], p3/m, z17.s
+// CHECK-INST: mov za1h.s[w12, 1], p3/m, z17.s
// CHECK-ENCODING: [0x25,0x0e,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 80 c0 <unknown>
-mov za0h.s[w12, #1], p1/m, z1.s
-// CHECK-INST: mov za0h.s[w12, #1], p1/m, z1.s
+mov za0h.s[w12, 1], p1/m, z1.s
+// CHECK-INST: mov za0h.s[w12, 1], p1/m, z1.s
// CHECK-ENCODING: [0x21,0x04,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 80 c0 <unknown>
-mov za2h.s[w14, #0], p5/m, z19.s
-// CHECK-INST: mov za2h.s[w14, #0], p5/m, z19.s
+mov za2h.s[w14, 0], p5/m, z19.s
+// CHECK-INST: mov za2h.s[w14, 0], p5/m, z19.s
// CHECK-ENCODING: [0x68,0x56,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 80 c0 <unknown>
-mov za0h.s[w12, #0], p6/m, z12.s
-// CHECK-INST: mov za0h.s[w12, #0], p6/m, z12.s
+mov za0h.s[w12, 0], p6/m, z12.s
+// CHECK-INST: mov za0h.s[w12, 0], p6/m, z12.s
// CHECK-ENCODING: [0x80,0x19,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 80 c0 <unknown>
-mov za0h.s[w14, #1], p2/m, z1.s
-// CHECK-INST: mov za0h.s[w14, #1], p2/m, z1.s
+mov za0h.s[w14, 1], p2/m, z1.s
+// CHECK-INST: mov za0h.s[w14, 1], p2/m, z1.s
// CHECK-ENCODING: [0x21,0x48,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 80 c0 <unknown>
-mov za3h.s[w12, #1], p2/m, z22.s
-// CHECK-INST: mov za3h.s[w12, #1], p2/m, z22.s
+mov za3h.s[w12, 1], p2/m, z22.s
+// CHECK-INST: mov za3h.s[w12, 1], p2/m, z22.s
// CHECK-ENCODING: [0xcd,0x0a,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 80 c0 <unknown>
-mov za0h.s[w15, #2], p5/m, z9.s
-// CHECK-INST: mov za0h.s[w15, #2], p5/m, z9.s
+mov za0h.s[w15, 2], p5/m, z9.s
+// CHECK-INST: mov za0h.s[w15, 2], p5/m, z9.s
// CHECK-ENCODING: [0x22,0x75,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 80 c0 <unknown>
-mov za1h.s[w13, #3], p2/m, z12.s
-// CHECK-INST: mov za1h.s[w13, #3], p2/m, z12.s
+mov za1h.s[w13, 3], p2/m, z12.s
+// CHECK-INST: mov za1h.s[w13, 3], p2/m, z12.s
// CHECK-ENCODING: [0x87,0x29,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 80 c0 <unknown>
@@ -2250,148 +2250,148 @@ mov za1h.s[w13, #3], p2/m, z12.s
// --------------------------------------------------------------------------//
// Insert, vector to tile, vertical, 32-bit
-mova za0v.s[w12, #0], p0/m, z0.s
-// CHECK-INST: mov za0v.s[w12, #0], p0/m, z0.s
+mova za0v.s[w12, 0], p0/m, z0.s
+// CHECK-INST: mov za0v.s[w12, 0], p0/m, z0.s
// CHECK-ENCODING: [0x00,0x80,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 80 c0 <unknown>
-mova za1v.s[w14, #1], p5/m, z10.s
-// CHECK-INST: mov za1v.s[w14, #1], p5/m, z10.s
+mova za1v.s[w14, 1], p5/m, z10.s
+// CHECK-INST: mov za1v.s[w14, 1], p5/m, z10.s
// CHECK-ENCODING: [0x45,0xd5,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 80 c0 <unknown>
-mova za1v.s[w15, #3], p3/m, z13.s
-// CHECK-INST: mov za1v.s[w15, #3], p3/m, z13.s
+mova za1v.s[w15, 3], p3/m, z13.s
+// CHECK-INST: mov za1v.s[w15, 3], p3/m, z13.s
// CHECK-ENCODING: [0xa7,0xed,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 80 c0 <unknown>
-mova za3v.s[w15, #3], p7/m, z31.s
-// CHECK-INST: mov za3v.s[w15, #3], p7/m, z31.s
+mova za3v.s[w15, 3], p7/m, z31.s
+// CHECK-INST: mov za3v.s[w15, 3], p7/m, z31.s
// CHECK-ENCODING: [0xef,0xff,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 80 c0 <unknown>
-mova za1v.s[w12, #1], p3/m, z17.s
-// CHECK-INST: mov za1v.s[w12, #1], p3/m, z17.s
+mova za1v.s[w12, 1], p3/m, z17.s
+// CHECK-INST: mov za1v.s[w12, 1], p3/m, z17.s
// CHECK-ENCODING: [0x25,0x8e,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 80 c0 <unknown>
-mova za0v.s[w12, #1], p1/m, z1.s
-// CHECK-INST: mov za0v.s[w12, #1], p1/m, z1.s
+mova za0v.s[w12, 1], p1/m, z1.s
+// CHECK-INST: mov za0v.s[w12, 1], p1/m, z1.s
// CHECK-ENCODING: [0x21,0x84,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 80 c0 <unknown>
-mova za2v.s[w14, #0], p5/m, z19.s
-// CHECK-INST: mov za2v.s[w14, #0], p5/m, z19.s
+mova za2v.s[w14, 0], p5/m, z19.s
+// CHECK-INST: mov za2v.s[w14, 0], p5/m, z19.s
// CHECK-ENCODING: [0x68,0xd6,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 80 c0 <unknown>
-mova za0v.s[w12, #0], p6/m, z12.s
-// CHECK-INST: mov za0v.s[w12, #0], p6/m, z12.s
+mova za0v.s[w12, 0], p6/m, z12.s
+// CHECK-INST: mov za0v.s[w12, 0], p6/m, z12.s
// CHECK-ENCODING: [0x80,0x99,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 80 c0 <unknown>
-mova za0v.s[w14, #1], p2/m, z1.s
-// CHECK-INST: mov za0v.s[w14, #1], p2/m, z1.s
+mova za0v.s[w14, 1], p2/m, z1.s
+// CHECK-INST: mov za0v.s[w14, 1], p2/m, z1.s
// CHECK-ENCODING: [0x21,0xc8,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 80 c0 <unknown>
-mova za3v.s[w12, #1], p2/m, z22.s
-// CHECK-INST: mov za3v.s[w12, #1], p2/m, z22.s
+mova za3v.s[w12, 1], p2/m, z22.s
+// CHECK-INST: mov za3v.s[w12, 1], p2/m, z22.s
// CHECK-ENCODING: [0xcd,0x8a,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 80 c0 <unknown>
-mova za0v.s[w15, #2], p5/m, z9.s
-// CHECK-INST: mov za0v.s[w15, #2], p5/m, z9.s
+mova za0v.s[w15, 2], p5/m, z9.s
+// CHECK-INST: mov za0v.s[w15, 2], p5/m, z9.s
// CHECK-ENCODING: [0x22,0xf5,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 80 c0 <unknown>
-mova za1v.s[w13, #3], p2/m, z12.s
-// CHECK-INST: mov za1v.s[w13, #3], p2/m, z12.s
+mova za1v.s[w13, 3], p2/m, z12.s
+// CHECK-INST: mov za1v.s[w13, 3], p2/m, z12.s
// CHECK-ENCODING: [0x87,0xa9,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 80 c0 <unknown>
// Aliases
-mov za0v.s[w12, #0], p0/m, z0.s
-// CHECK-INST: mov za0v.s[w12, #0], p0/m, z0.s
+mov za0v.s[w12, 0], p0/m, z0.s
+// CHECK-INST: mov za0v.s[w12, 0], p0/m, z0.s
// CHECK-ENCODING: [0x00,0x80,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 80 c0 <unknown>
-mov za1v.s[w14, #1], p5/m, z10.s
-// CHECK-INST: mov za1v.s[w14, #1], p5/m, z10.s
+mov za1v.s[w14, 1], p5/m, z10.s
+// CHECK-INST: mov za1v.s[w14, 1], p5/m, z10.s
// CHECK-ENCODING: [0x45,0xd5,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 80 c0 <unknown>
-mov za1v.s[w15, #3], p3/m, z13.s
-// CHECK-INST: mov za1v.s[w15, #3], p3/m, z13.s
+mov za1v.s[w15, 3], p3/m, z13.s
+// CHECK-INST: mov za1v.s[w15, 3], p3/m, z13.s
// CHECK-ENCODING: [0xa7,0xed,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 80 c0 <unknown>
-mov za3v.s[w15, #3], p7/m, z31.s
-// CHECK-INST: mov za3v.s[w15, #3], p7/m, z31.s
+mov za3v.s[w15, 3], p7/m, z31.s
+// CHECK-INST: mov za3v.s[w15, 3], p7/m, z31.s
// CHECK-ENCODING: [0xef,0xff,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 80 c0 <unknown>
-mov za1v.s[w12, #1], p3/m, z17.s
-// CHECK-INST: mov za1v.s[w12, #1], p3/m, z17.s
+mov za1v.s[w12, 1], p3/m, z17.s
+// CHECK-INST: mov za1v.s[w12, 1], p3/m, z17.s
// CHECK-ENCODING: [0x25,0x8e,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 80 c0 <unknown>
-mov za0v.s[w12, #1], p1/m, z1.s
-// CHECK-INST: mov za0v.s[w12, #1], p1/m, z1.s
+mov za0v.s[w12, 1], p1/m, z1.s
+// CHECK-INST: mov za0v.s[w12, 1], p1/m, z1.s
// CHECK-ENCODING: [0x21,0x84,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 80 c0 <unknown>
-mov za2v.s[w14, #0], p5/m, z19.s
-// CHECK-INST: mov za2v.s[w14, #0], p5/m, z19.s
+mov za2v.s[w14, 0], p5/m, z19.s
+// CHECK-INST: mov za2v.s[w14, 0], p5/m, z19.s
// CHECK-ENCODING: [0x68,0xd6,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 80 c0 <unknown>
-mov za0v.s[w12, #0], p6/m, z12.s
-// CHECK-INST: mov za0v.s[w12, #0], p6/m, z12.s
+mov za0v.s[w12, 0], p6/m, z12.s
+// CHECK-INST: mov za0v.s[w12, 0], p6/m, z12.s
// CHECK-ENCODING: [0x80,0x99,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 80 c0 <unknown>
-mov za0v.s[w14, #1], p2/m, z1.s
-// CHECK-INST: mov za0v.s[w14, #1], p2/m, z1.s
+mov za0v.s[w14, 1], p2/m, z1.s
+// CHECK-INST: mov za0v.s[w14, 1], p2/m, z1.s
// CHECK-ENCODING: [0x21,0xc8,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 80 c0 <unknown>
-mov za3v.s[w12, #1], p2/m, z22.s
-// CHECK-INST: mov za3v.s[w12, #1], p2/m, z22.s
+mov za3v.s[w12, 1], p2/m, z22.s
+// CHECK-INST: mov za3v.s[w12, 1], p2/m, z22.s
// CHECK-ENCODING: [0xcd,0x8a,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 80 c0 <unknown>
-mov za0v.s[w15, #2], p5/m, z9.s
-// CHECK-INST: mov za0v.s[w15, #2], p5/m, z9.s
+mov za0v.s[w15, 2], p5/m, z9.s
+// CHECK-INST: mov za0v.s[w15, 2], p5/m, z9.s
// CHECK-ENCODING: [0x22,0xf5,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 80 c0 <unknown>
-mov za1v.s[w13, #3], p2/m, z12.s
-// CHECK-INST: mov za1v.s[w13, #3], p2/m, z12.s
+mov za1v.s[w13, 3], p2/m, z12.s
+// CHECK-INST: mov za1v.s[w13, 3], p2/m, z12.s
// CHECK-ENCODING: [0x87,0xa9,0x80,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 80 c0 <unknown>
@@ -2399,148 +2399,148 @@ mov za1v.s[w13, #3], p2/m, z12.s
// --------------------------------------------------------------------------//
// Insert, vector to tile, horizontal, 64-bit
-mova za0h.d[w12, #0], p0/m, z0.d
-// CHECK-INST: mov za0h.d[w12, #0], p0/m, z0.d
+mova za0h.d[w12, 0], p0/m, z0.d
+// CHECK-INST: mov za0h.d[w12, 0], p0/m, z0.d
// CHECK-ENCODING: [0x00,0x00,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 c0 c0 <unknown>
-mova za2h.d[w14, #1], p5/m, z10.d
-// CHECK-INST: mov za2h.d[w14, #1], p5/m, z10.d
+mova za2h.d[w14, 1], p5/m, z10.d
+// CHECK-INST: mov za2h.d[w14, 1], p5/m, z10.d
// CHECK-ENCODING: [0x45,0x55,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 c0 c0 <unknown>
-mova za3h.d[w15, #1], p3/m, z13.d
-// CHECK-INST: mov za3h.d[w15, #1], p3/m, z13.d
+mova za3h.d[w15, 1], p3/m, z13.d
+// CHECK-INST: mov za3h.d[w15, 1], p3/m, z13.d
// CHECK-ENCODING: [0xa7,0x6d,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d c0 c0 <unknown>
-mova za7h.d[w15, #1], p7/m, z31.d
-// CHECK-INST: mov za7h.d[w15, #1], p7/m, z31.d
+mova za7h.d[w15, 1], p7/m, z31.d
+// CHECK-INST: mov za7h.d[w15, 1], p7/m, z31.d
// CHECK-ENCODING: [0xef,0x7f,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f c0 c0 <unknown>
-mova za2h.d[w12, #1], p3/m, z17.d
-// CHECK-INST: mov za2h.d[w12, #1], p3/m, z17.d
+mova za2h.d[w12, 1], p3/m, z17.d
+// CHECK-INST: mov za2h.d[w12, 1], p3/m, z17.d
// CHECK-ENCODING: [0x25,0x0e,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e c0 c0 <unknown>
-mova za0h.d[w12, #1], p1/m, z1.d
-// CHECK-INST: mov za0h.d[w12, #1], p1/m, z1.d
+mova za0h.d[w12, 1], p1/m, z1.d
+// CHECK-INST: mov za0h.d[w12, 1], p1/m, z1.d
// CHECK-ENCODING: [0x21,0x04,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 c0 c0 <unknown>
-mova za4h.d[w14, #0], p5/m, z19.d
-// CHECK-INST: mov za4h.d[w14, #0], p5/m, z19.d
+mova za4h.d[w14, 0], p5/m, z19.d
+// CHECK-INST: mov za4h.d[w14, 0], p5/m, z19.d
// CHECK-ENCODING: [0x68,0x56,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 c0 c0 <unknown>
-mova za0h.d[w12, #0], p6/m, z12.d
-// CHECK-INST: mov za0h.d[w12, #0], p6/m, z12.d
+mova za0h.d[w12, 0], p6/m, z12.d
+// CHECK-INST: mov za0h.d[w12, 0], p6/m, z12.d
// CHECK-ENCODING: [0x80,0x19,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 c0 c0 <unknown>
-mova za0h.d[w14, #1], p2/m, z1.d
-// CHECK-INST: mov za0h.d[w14, #1], p2/m, z1.d
+mova za0h.d[w14, 1], p2/m, z1.d
+// CHECK-INST: mov za0h.d[w14, 1], p2/m, z1.d
// CHECK-ENCODING: [0x21,0x48,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 c0 c0 <unknown>
-mova za6h.d[w12, #1], p2/m, z22.d
-// CHECK-INST: mov za6h.d[w12, #1], p2/m, z22.d
+mova za6h.d[w12, 1], p2/m, z22.d
+// CHECK-INST: mov za6h.d[w12, 1], p2/m, z22.d
// CHECK-ENCODING: [0xcd,0x0a,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a c0 c0 <unknown>
-mova za1h.d[w15, #0], p5/m, z9.d
-// CHECK-INST: mov za1h.d[w15, #0], p5/m, z9.d
+mova za1h.d[w15, 0], p5/m, z9.d
+// CHECK-INST: mov za1h.d[w15, 0], p5/m, z9.d
// CHECK-ENCODING: [0x22,0x75,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 c0 c0 <unknown>
-mova za3h.d[w13, #1], p2/m, z12.d
-// CHECK-INST: mov za3h.d[w13, #1], p2/m, z12.d
+mova za3h.d[w13, 1], p2/m, z12.d
+// CHECK-INST: mov za3h.d[w13, 1], p2/m, z12.d
// CHECK-ENCODING: [0x87,0x29,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 c0 c0 <unknown>
// Aliases
-mov za0h.d[w12, #0], p0/m, z0.d
-// CHECK-INST: mov za0h.d[w12, #0], p0/m, z0.d
+mov za0h.d[w12, 0], p0/m, z0.d
+// CHECK-INST: mov za0h.d[w12, 0], p0/m, z0.d
// CHECK-ENCODING: [0x00,0x00,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 c0 c0 <unknown>
-mov za2h.d[w14, #1], p5/m, z10.d
-// CHECK-INST: mov za2h.d[w14, #1], p5/m, z10.d
+mov za2h.d[w14, 1], p5/m, z10.d
+// CHECK-INST: mov za2h.d[w14, 1], p5/m, z10.d
// CHECK-ENCODING: [0x45,0x55,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 c0 c0 <unknown>
-mov za3h.d[w15, #1], p3/m, z13.d
-// CHECK-INST: mov za3h.d[w15, #1], p3/m, z13.d
+mov za3h.d[w15, 1], p3/m, z13.d
+// CHECK-INST: mov za3h.d[w15, 1], p3/m, z13.d
// CHECK-ENCODING: [0xa7,0x6d,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d c0 c0 <unknown>
-mov za7h.d[w15, #1], p7/m, z31.d
-// CHECK-INST: mov za7h.d[w15, #1], p7/m, z31.d
+mov za7h.d[w15, 1], p7/m, z31.d
+// CHECK-INST: mov za7h.d[w15, 1], p7/m, z31.d
// CHECK-ENCODING: [0xef,0x7f,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f c0 c0 <unknown>
-mov za2h.d[w12, #1], p3/m, z17.d
-// CHECK-INST: mov za2h.d[w12, #1], p3/m, z17.d
+mov za2h.d[w12, 1], p3/m, z17.d
+// CHECK-INST: mov za2h.d[w12, 1], p3/m, z17.d
// CHECK-ENCODING: [0x25,0x0e,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e c0 c0 <unknown>
-mov za0h.d[w12, #1], p1/m, z1.d
-// CHECK-INST: mov za0h.d[w12, #1], p1/m, z1.d
+mov za0h.d[w12, 1], p1/m, z1.d
+// CHECK-INST: mov za0h.d[w12, 1], p1/m, z1.d
// CHECK-ENCODING: [0x21,0x04,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 c0 c0 <unknown>
-mov za4h.d[w14, #0], p5/m, z19.d
-// CHECK-INST: mov za4h.d[w14, #0], p5/m, z19.d
+mov za4h.d[w14, 0], p5/m, z19.d
+// CHECK-INST: mov za4h.d[w14, 0], p5/m, z19.d
// CHECK-ENCODING: [0x68,0x56,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 c0 c0 <unknown>
-mov za0h.d[w12, #0], p6/m, z12.d
-// CHECK-INST: mov za0h.d[w12, #0], p6/m, z12.d
+mov za0h.d[w12, 0], p6/m, z12.d
+// CHECK-INST: mov za0h.d[w12, 0], p6/m, z12.d
// CHECK-ENCODING: [0x80,0x19,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 c0 c0 <unknown>
-mov za0h.d[w14, #1], p2/m, z1.d
-// CHECK-INST: mov za0h.d[w14, #1], p2/m, z1.d
+mov za0h.d[w14, 1], p2/m, z1.d
+// CHECK-INST: mov za0h.d[w14, 1], p2/m, z1.d
// CHECK-ENCODING: [0x21,0x48,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 c0 c0 <unknown>
-mov za6h.d[w12, #1], p2/m, z22.d
-// CHECK-INST: mov za6h.d[w12, #1], p2/m, z22.d
+mov za6h.d[w12, 1], p2/m, z22.d
+// CHECK-INST: mov za6h.d[w12, 1], p2/m, z22.d
// CHECK-ENCODING: [0xcd,0x0a,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a c0 c0 <unknown>
-mov za1h.d[w15, #0], p5/m, z9.d
-// CHECK-INST: mov za1h.d[w15, #0], p5/m, z9.d
+mov za1h.d[w15, 0], p5/m, z9.d
+// CHECK-INST: mov za1h.d[w15, 0], p5/m, z9.d
// CHECK-ENCODING: [0x22,0x75,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 c0 c0 <unknown>
-mov za3h.d[w13, #1], p2/m, z12.d
-// CHECK-INST: mov za3h.d[w13, #1], p2/m, z12.d
+mov za3h.d[w13, 1], p2/m, z12.d
+// CHECK-INST: mov za3h.d[w13, 1], p2/m, z12.d
// CHECK-ENCODING: [0x87,0x29,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 c0 c0 <unknown>
@@ -2548,148 +2548,148 @@ mov za3h.d[w13, #1], p2/m, z12.d
// --------------------------------------------------------------------------//
// Insert, vector to tile, vertical, 64-bit
-mova za0v.d[w12, #0], p0/m, z0.d
-// CHECK-INST: mov za0v.d[w12, #0], p0/m, z0.d
+mova za0v.d[w12, 0], p0/m, z0.d
+// CHECK-INST: mov za0v.d[w12, 0], p0/m, z0.d
// CHECK-ENCODING: [0x00,0x80,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 c0 c0 <unknown>
-mova za2v.d[w14, #1], p5/m, z10.d
-// CHECK-INST: mov za2v.d[w14, #1], p5/m, z10.d
+mova za2v.d[w14, 1], p5/m, z10.d
+// CHECK-INST: mov za2v.d[w14, 1], p5/m, z10.d
// CHECK-ENCODING: [0x45,0xd5,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 c0 c0 <unknown>
-mova za3v.d[w15, #1], p3/m, z13.d
-// CHECK-INST: mov za3v.d[w15, #1], p3/m, z13.d
+mova za3v.d[w15, 1], p3/m, z13.d
+// CHECK-INST: mov za3v.d[w15, 1], p3/m, z13.d
// CHECK-ENCODING: [0xa7,0xed,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed c0 c0 <unknown>
-mova za7v.d[w15, #1], p7/m, z31.d
-// CHECK-INST: mov za7v.d[w15, #1], p7/m, z31.d
+mova za7v.d[w15, 1], p7/m, z31.d
+// CHECK-INST: mov za7v.d[w15, 1], p7/m, z31.d
// CHECK-ENCODING: [0xef,0xff,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff c0 c0 <unknown>
-mova za2v.d[w12, #1], p3/m, z17.d
-// CHECK-INST: mov za2v.d[w12, #1], p3/m, z17.d
+mova za2v.d[w12, 1], p3/m, z17.d
+// CHECK-INST: mov za2v.d[w12, 1], p3/m, z17.d
// CHECK-ENCODING: [0x25,0x8e,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e c0 c0 <unknown>
-mova za0v.d[w12, #1], p1/m, z1.d
-// CHECK-INST: mov za0v.d[w12, #1], p1/m, z1.d
+mova za0v.d[w12, 1], p1/m, z1.d
+// CHECK-INST: mov za0v.d[w12, 1], p1/m, z1.d
// CHECK-ENCODING: [0x21,0x84,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 c0 c0 <unknown>
-mova za4v.d[w14, #0], p5/m, z19.d
-// CHECK-INST: mov za4v.d[w14, #0], p5/m, z19.d
+mova za4v.d[w14, 0], p5/m, z19.d
+// CHECK-INST: mov za4v.d[w14, 0], p5/m, z19.d
// CHECK-ENCODING: [0x68,0xd6,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 c0 c0 <unknown>
-mova za0v.d[w12, #0], p6/m, z12.d
-// CHECK-INST: mov za0v.d[w12, #0], p6/m, z12.d
+mova za0v.d[w12, 0], p6/m, z12.d
+// CHECK-INST: mov za0v.d[w12, 0], p6/m, z12.d
// CHECK-ENCODING: [0x80,0x99,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 c0 c0 <unknown>
-mova za0v.d[w14, #1], p2/m, z1.d
-// CHECK-INST: mov za0v.d[w14, #1], p2/m, z1.d
+mova za0v.d[w14, 1], p2/m, z1.d
+// CHECK-INST: mov za0v.d[w14, 1], p2/m, z1.d
// CHECK-ENCODING: [0x21,0xc8,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 c0 c0 <unknown>
-mova za6v.d[w12, #1], p2/m, z22.d
-// CHECK-INST: mov za6v.d[w12, #1], p2/m, z22.d
+mova za6v.d[w12, 1], p2/m, z22.d
+// CHECK-INST: mov za6v.d[w12, 1], p2/m, z22.d
// CHECK-ENCODING: [0xcd,0x8a,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a c0 c0 <unknown>
-mova za1v.d[w15, #0], p5/m, z9.d
-// CHECK-INST: mov za1v.d[w15, #0], p5/m, z9.d
+mova za1v.d[w15, 0], p5/m, z9.d
+// CHECK-INST: mov za1v.d[w15, 0], p5/m, z9.d
// CHECK-ENCODING: [0x22,0xf5,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 c0 c0 <unknown>
-mova za3v.d[w13, #1], p2/m, z12.d
-// CHECK-INST: mov za3v.d[w13, #1], p2/m, z12.d
+mova za3v.d[w13, 1], p2/m, z12.d
+// CHECK-INST: mov za3v.d[w13, 1], p2/m, z12.d
// CHECK-ENCODING: [0x87,0xa9,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 c0 c0 <unknown>
// Aliases
-mov za0v.d[w12, #0], p0/m, z0.d
-// CHECK-INST: mov za0v.d[w12, #0], p0/m, z0.d
+mov za0v.d[w12, 0], p0/m, z0.d
+// CHECK-INST: mov za0v.d[w12, 0], p0/m, z0.d
// CHECK-ENCODING: [0x00,0x80,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 c0 c0 <unknown>
-mov za2v.d[w14, #1], p5/m, z10.d
-// CHECK-INST: mov za2v.d[w14, #1], p5/m, z10.d
+mov za2v.d[w14, 1], p5/m, z10.d
+// CHECK-INST: mov za2v.d[w14, 1], p5/m, z10.d
// CHECK-ENCODING: [0x45,0xd5,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 c0 c0 <unknown>
-mov za3v.d[w15, #1], p3/m, z13.d
-// CHECK-INST: mov za3v.d[w15, #1], p3/m, z13.d
+mov za3v.d[w15, 1], p3/m, z13.d
+// CHECK-INST: mov za3v.d[w15, 1], p3/m, z13.d
// CHECK-ENCODING: [0xa7,0xed,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed c0 c0 <unknown>
-mov za7v.d[w15, #1], p7/m, z31.d
-// CHECK-INST: mov za7v.d[w15, #1], p7/m, z31.d
+mov za7v.d[w15, 1], p7/m, z31.d
+// CHECK-INST: mov za7v.d[w15, 1], p7/m, z31.d
// CHECK-ENCODING: [0xef,0xff,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff c0 c0 <unknown>
-mov za2v.d[w12, #1], p3/m, z17.d
-// CHECK-INST: mov za2v.d[w12, #1], p3/m, z17.d
+mov za2v.d[w12, 1], p3/m, z17.d
+// CHECK-INST: mov za2v.d[w12, 1], p3/m, z17.d
// CHECK-ENCODING: [0x25,0x8e,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e c0 c0 <unknown>
-mov za0v.d[w12, #1], p1/m, z1.d
-// CHECK-INST: mov za0v.d[w12, #1], p1/m, z1.d
+mov za0v.d[w12, 1], p1/m, z1.d
+// CHECK-INST: mov za0v.d[w12, 1], p1/m, z1.d
// CHECK-ENCODING: [0x21,0x84,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 c0 c0 <unknown>
-mov za4v.d[w14, #0], p5/m, z19.d
-// CHECK-INST: mov za4v.d[w14, #0], p5/m, z19.d
+mov za4v.d[w14, 0], p5/m, z19.d
+// CHECK-INST: mov za4v.d[w14, 0], p5/m, z19.d
// CHECK-ENCODING: [0x68,0xd6,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 c0 c0 <unknown>
-mov za0v.d[w12, #0], p6/m, z12.d
-// CHECK-INST: mov za0v.d[w12, #0], p6/m, z12.d
+mov za0v.d[w12, 0], p6/m, z12.d
+// CHECK-INST: mov za0v.d[w12, 0], p6/m, z12.d
// CHECK-ENCODING: [0x80,0x99,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 c0 c0 <unknown>
-mov za0v.d[w14, #1], p2/m, z1.d
-// CHECK-INST: mov za0v.d[w14, #1], p2/m, z1.d
+mov za0v.d[w14, 1], p2/m, z1.d
+// CHECK-INST: mov za0v.d[w14, 1], p2/m, z1.d
// CHECK-ENCODING: [0x21,0xc8,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 c0 c0 <unknown>
-mov za6v.d[w12, #1], p2/m, z22.d
-// CHECK-INST: mov za6v.d[w12, #1], p2/m, z22.d
+mov za6v.d[w12, 1], p2/m, z22.d
+// CHECK-INST: mov za6v.d[w12, 1], p2/m, z22.d
// CHECK-ENCODING: [0xcd,0x8a,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a c0 c0 <unknown>
-mov za1v.d[w15, #0], p5/m, z9.d
-// CHECK-INST: mov za1v.d[w15, #0], p5/m, z9.d
+mov za1v.d[w15, 0], p5/m, z9.d
+// CHECK-INST: mov za1v.d[w15, 0], p5/m, z9.d
// CHECK-ENCODING: [0x22,0xf5,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 c0 c0 <unknown>
-mov za3v.d[w13, #1], p2/m, z12.d
-// CHECK-INST: mov za3v.d[w13, #1], p2/m, z12.d
+mov za3v.d[w13, 1], p2/m, z12.d
+// CHECK-INST: mov za3v.d[w13, 1], p2/m, z12.d
// CHECK-ENCODING: [0x87,0xa9,0xc0,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 c0 c0 <unknown>
@@ -2697,148 +2697,148 @@ mov za3v.d[w13, #1], p2/m, z12.d
// --------------------------------------------------------------------------//
// Insert, vector to tile, horizontal, 128-bit
-mova za0h.q[w12], p0/m, z0.q
-// CHECK-INST: mov za0h.q[w12], p0/m, z0.q
+mova za0h.q[w12, 0], p0/m, z0.q
+// CHECK-INST: mov za0h.q[w12, 0], p0/m, z0.q
// CHECK-ENCODING: [0x00,0x00,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 c1 c0 <unknown>
-mova za5h.q[w14], p5/m, z10.q
-// CHECK-INST: mov za5h.q[w14], p5/m, z10.q
+mova za5h.q[w14, 0], p5/m, z10.q
+// CHECK-INST: mov za5h.q[w14, 0], p5/m, z10.q
// CHECK-ENCODING: [0x45,0x55,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 c1 c0 <unknown>
-mova za7h.q[w15], p3/m, z13.q
-// CHECK-INST: mov za7h.q[w15], p3/m, z13.q
+mova za7h.q[w15, 0], p3/m, z13.q
+// CHECK-INST: mov za7h.q[w15, 0], p3/m, z13.q
// CHECK-ENCODING: [0xa7,0x6d,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d c1 c0 <unknown>
-mova za15h.q[w15], p7/m, z31.q
-// CHECK-INST: mov za15h.q[w15], p7/m, z31.q
+mova za15h.q[w15, 0], p7/m, z31.q
+// CHECK-INST: mov za15h.q[w15, 0], p7/m, z31.q
// CHECK-ENCODING: [0xef,0x7f,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f c1 c0 <unknown>
-mova za5h.q[w12], p3/m, z17.q
-// CHECK-INST: mov za5h.q[w12], p3/m, z17.q
+mova za5h.q[w12, 0], p3/m, z17.q
+// CHECK-INST: mov za5h.q[w12, 0], p3/m, z17.q
// CHECK-ENCODING: [0x25,0x0e,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e c1 c0 <unknown>
-mova za1h.q[w12], p1/m, z1.q
-// CHECK-INST: mov za1h.q[w12], p1/m, z1.q
+mova za1h.q[w12, 0], p1/m, z1.q
+// CHECK-INST: mov za1h.q[w12, 0], p1/m, z1.q
// CHECK-ENCODING: [0x21,0x04,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 c1 c0 <unknown>
-mova za8h.q[w14], p5/m, z19.q
-// CHECK-INST: mov za8h.q[w14], p5/m, z19.q
+mova za8h.q[w14, 0], p5/m, z19.q
+// CHECK-INST: mov za8h.q[w14, 0], p5/m, z19.q
// CHECK-ENCODING: [0x68,0x56,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 c1 c0 <unknown>
-mova za0h.q[w12], p6/m, z12.q
-// CHECK-INST: mov za0h.q[w12], p6/m, z12.q
+mova za0h.q[w12, 0], p6/m, z12.q
+// CHECK-INST: mov za0h.q[w12, 0], p6/m, z12.q
// CHECK-ENCODING: [0x80,0x19,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 c1 c0 <unknown>
-mova za1h.q[w14], p2/m, z1.q
-// CHECK-INST: mov za1h.q[w14], p2/m, z1.q
+mova za1h.q[w14, 0], p2/m, z1.q
+// CHECK-INST: mov za1h.q[w14, 0], p2/m, z1.q
// CHECK-ENCODING: [0x21,0x48,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 c1 c0 <unknown>
-mova za13h.q[w12], p2/m, z22.q
-// CHECK-INST: mov za13h.q[w12], p2/m, z22.q
+mova za13h.q[w12, 0], p2/m, z22.q
+// CHECK-INST: mov za13h.q[w12, 0], p2/m, z22.q
// CHECK-ENCODING: [0xcd,0x0a,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a c1 c0 <unknown>
-mova za2h.q[w15], p5/m, z9.q
-// CHECK-INST: mov za2h.q[w15], p5/m, z9.q
+mova za2h.q[w15, 0], p5/m, z9.q
+// CHECK-INST: mov za2h.q[w15, 0], p5/m, z9.q
// CHECK-ENCODING: [0x22,0x75,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 c1 c0 <unknown>
-mova za7h.q[w13], p2/m, z12.q
-// CHECK-INST: mov za7h.q[w13], p2/m, z12.q
+mova za7h.q[w13, 0], p2/m, z12.q
+// CHECK-INST: mov za7h.q[w13, 0], p2/m, z12.q
// CHECK-ENCODING: [0x87,0x29,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 c1 c0 <unknown>
// Aliases
-mov za0h.q[w12], p0/m, z0.q
-// CHECK-INST: mov za0h.q[w12], p0/m, z0.q
+mov za0h.q[w12, 0], p0/m, z0.q
+// CHECK-INST: mov za0h.q[w12, 0], p0/m, z0.q
// CHECK-ENCODING: [0x00,0x00,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 c1 c0 <unknown>
-mov za5h.q[w14], p5/m, z10.q
-// CHECK-INST: mov za5h.q[w14], p5/m, z10.q
+mov za5h.q[w14, 0], p5/m, z10.q
+// CHECK-INST: mov za5h.q[w14, 0], p5/m, z10.q
// CHECK-ENCODING: [0x45,0x55,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 c1 c0 <unknown>
-mov za7h.q[w15], p3/m, z13.q
-// CHECK-INST: mov za7h.q[w15], p3/m, z13.q
+mov za7h.q[w15, 0], p3/m, z13.q
+// CHECK-INST: mov za7h.q[w15, 0], p3/m, z13.q
// CHECK-ENCODING: [0xa7,0x6d,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d c1 c0 <unknown>
-mov za15h.q[w15], p7/m, z31.q
-// CHECK-INST: mov za15h.q[w15], p7/m, z31.q
+mov za15h.q[w15, 0], p7/m, z31.q
+// CHECK-INST: mov za15h.q[w15, 0], p7/m, z31.q
// CHECK-ENCODING: [0xef,0x7f,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f c1 c0 <unknown>
-mov za5h.q[w12], p3/m, z17.q
-// CHECK-INST: mov za5h.q[w12], p3/m, z17.q
+mov za5h.q[w12, 0], p3/m, z17.q
+// CHECK-INST: mov za5h.q[w12, 0], p3/m, z17.q
// CHECK-ENCODING: [0x25,0x0e,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e c1 c0 <unknown>
-mov za1h.q[w12], p1/m, z1.q
-// CHECK-INST: mov za1h.q[w12], p1/m, z1.q
+mov za1h.q[w12, 0], p1/m, z1.q
+// CHECK-INST: mov za1h.q[w12, 0], p1/m, z1.q
// CHECK-ENCODING: [0x21,0x04,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 c1 c0 <unknown>
-mov za8h.q[w14], p5/m, z19.q
-// CHECK-INST: mov za8h.q[w14], p5/m, z19.q
+mov za8h.q[w14, 0], p5/m, z19.q
+// CHECK-INST: mov za8h.q[w14, 0], p5/m, z19.q
// CHECK-ENCODING: [0x68,0x56,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 c1 c0 <unknown>
-mov za0h.q[w12], p6/m, z12.q
-// CHECK-INST: mov za0h.q[w12], p6/m, z12.q
+mov za0h.q[w12, 0], p6/m, z12.q
+// CHECK-INST: mov za0h.q[w12, 0], p6/m, z12.q
// CHECK-ENCODING: [0x80,0x19,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 c1 c0 <unknown>
-mov za1h.q[w14], p2/m, z1.q
-// CHECK-INST: mov za1h.q[w14], p2/m, z1.q
+mov za1h.q[w14, 0], p2/m, z1.q
+// CHECK-INST: mov za1h.q[w14, 0], p2/m, z1.q
// CHECK-ENCODING: [0x21,0x48,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 c1 c0 <unknown>
-mov za13h.q[w12], p2/m, z22.q
-// CHECK-INST: mov za13h.q[w12], p2/m, z22.q
+mov za13h.q[w12, 0], p2/m, z22.q
+// CHECK-INST: mov za13h.q[w12, 0], p2/m, z22.q
// CHECK-ENCODING: [0xcd,0x0a,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a c1 c0 <unknown>
-mov za2h.q[w15], p5/m, z9.q
-// CHECK-INST: mov za2h.q[w15], p5/m, z9.q
+mov za2h.q[w15, 0], p5/m, z9.q
+// CHECK-INST: mov za2h.q[w15, 0], p5/m, z9.q
// CHECK-ENCODING: [0x22,0x75,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 c1 c0 <unknown>
-mov za7h.q[w13], p2/m, z12.q
-// CHECK-INST: mov za7h.q[w13], p2/m, z12.q
+mov za7h.q[w13, 0], p2/m, z12.q
+// CHECK-INST: mov za7h.q[w13, 0], p2/m, z12.q
// CHECK-ENCODING: [0x87,0x29,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 c1 c0 <unknown>
@@ -2846,148 +2846,148 @@ mov za7h.q[w13], p2/m, z12.q
// --------------------------------------------------------------------------//
// Insert, vector to tile, vertical, 128-bit
-mova za0v.q[w12], p0/m, z0.q
-// CHECK-INST: mov za0v.q[w12], p0/m, z0.q
+mova za0v.q[w12, 0], p0/m, z0.q
+// CHECK-INST: mov za0v.q[w12, 0], p0/m, z0.q
// CHECK-ENCODING: [0x00,0x80,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 c1 c0 <unknown>
-mova za5v.q[w14], p5/m, z10.q
-// CHECK-INST: mov za5v.q[w14], p5/m, z10.q
+mova za5v.q[w14, 0], p5/m, z10.q
+// CHECK-INST: mov za5v.q[w14, 0], p5/m, z10.q
// CHECK-ENCODING: [0x45,0xd5,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 c1 c0 <unknown>
-mova za7v.q[w15], p3/m, z13.q
-// CHECK-INST: mov za7v.q[w15], p3/m, z13.q
+mova za7v.q[w15, 0], p3/m, z13.q
+// CHECK-INST: mov za7v.q[w15, 0], p3/m, z13.q
// CHECK-ENCODING: [0xa7,0xed,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed c1 c0 <unknown>
-mova za15v.q[w15], p7/m, z31.q
-// CHECK-INST: mov za15v.q[w15], p7/m, z31.q
+mova za15v.q[w15, 0], p7/m, z31.q
+// CHECK-INST: mov za15v.q[w15, 0], p7/m, z31.q
// CHECK-ENCODING: [0xef,0xff,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff c1 c0 <unknown>
-mova za5v.q[w12], p3/m, z17.q
-// CHECK-INST: mov za5v.q[w12], p3/m, z17.q
+mova za5v.q[w12, 0], p3/m, z17.q
+// CHECK-INST: mov za5v.q[w12, 0], p3/m, z17.q
// CHECK-ENCODING: [0x25,0x8e,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e c1 c0 <unknown>
-mova za1v.q[w12], p1/m, z1.q
-// CHECK-INST: mov za1v.q[w12], p1/m, z1.q
+mova za1v.q[w12, 0], p1/m, z1.q
+// CHECK-INST: mov za1v.q[w12, 0], p1/m, z1.q
// CHECK-ENCODING: [0x21,0x84,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 c1 c0 <unknown>
-mova za8v.q[w14], p5/m, z19.q
-// CHECK-INST: mov za8v.q[w14], p5/m, z19.q
+mova za8v.q[w14, 0], p5/m, z19.q
+// CHECK-INST: mov za8v.q[w14, 0], p5/m, z19.q
// CHECK-ENCODING: [0x68,0xd6,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 c1 c0 <unknown>
-mova za0v.q[w12], p6/m, z12.q
-// CHECK-INST: mov za0v.q[w12], p6/m, z12.q
+mova za0v.q[w12, 0], p6/m, z12.q
+// CHECK-INST: mov za0v.q[w12, 0], p6/m, z12.q
// CHECK-ENCODING: [0x80,0x99,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 c1 c0 <unknown>
-mova za1v.q[w14], p2/m, z1.q
-// CHECK-INST: mov za1v.q[w14], p2/m, z1.q
+mova za1v.q[w14, 0], p2/m, z1.q
+// CHECK-INST: mov za1v.q[w14, 0], p2/m, z1.q
// CHECK-ENCODING: [0x21,0xc8,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 c1 c0 <unknown>
-mova za13v.q[w12], p2/m, z22.q
-// CHECK-INST: mov za13v.q[w12], p2/m, z22.q
+mova za13v.q[w12, 0], p2/m, z22.q
+// CHECK-INST: mov za13v.q[w12, 0], p2/m, z22.q
// CHECK-ENCODING: [0xcd,0x8a,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a c1 c0 <unknown>
-mova za2v.q[w15], p5/m, z9.q
-// CHECK-INST: mov za2v.q[w15], p5/m, z9.q
+mova za2v.q[w15, 0], p5/m, z9.q
+// CHECK-INST: mov za2v.q[w15, 0], p5/m, z9.q
// CHECK-ENCODING: [0x22,0xf5,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 c1 c0 <unknown>
-mova za7v.q[w13], p2/m, z12.q
-// CHECK-INST: mov za7v.q[w13], p2/m, z12.q
+mova za7v.q[w13, 0], p2/m, z12.q
+// CHECK-INST: mov za7v.q[w13, 0], p2/m, z12.q
// CHECK-ENCODING: [0x87,0xa9,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 c1 c0 <unknown>
// Aliases
-mov za0v.q[w12], p0/m, z0.q
-// CHECK-INST: mov za0v.q[w12], p0/m, z0.q
+mov za0v.q[w12, 0], p0/m, z0.q
+// CHECK-INST: mov za0v.q[w12, 0], p0/m, z0.q
// CHECK-ENCODING: [0x00,0x80,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 c1 c0 <unknown>
-mov za5v.q[w14], p5/m, z10.q
-// CHECK-INST: mov za5v.q[w14], p5/m, z10.q
+mov za5v.q[w14, 0], p5/m, z10.q
+// CHECK-INST: mov za5v.q[w14, 0], p5/m, z10.q
// CHECK-ENCODING: [0x45,0xd5,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 c1 c0 <unknown>
-mov za7v.q[w15], p3/m, z13.q
-// CHECK-INST: mov za7v.q[w15], p3/m, z13.q
+mov za7v.q[w15, 0], p3/m, z13.q
+// CHECK-INST: mov za7v.q[w15, 0], p3/m, z13.q
// CHECK-ENCODING: [0xa7,0xed,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed c1 c0 <unknown>
-mov za15v.q[w15], p7/m, z31.q
-// CHECK-INST: mov za15v.q[w15], p7/m, z31.q
+mov za15v.q[w15, 0], p7/m, z31.q
+// CHECK-INST: mov za15v.q[w15, 0], p7/m, z31.q
// CHECK-ENCODING: [0xef,0xff,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff c1 c0 <unknown>
-mov za5v.q[w12], p3/m, z17.q
-// CHECK-INST: mov za5v.q[w12], p3/m, z17.q
+mov za5v.q[w12, 0], p3/m, z17.q
+// CHECK-INST: mov za5v.q[w12, 0], p3/m, z17.q
// CHECK-ENCODING: [0x25,0x8e,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e c1 c0 <unknown>
-mov za1v.q[w12], p1/m, z1.q
-// CHECK-INST: mov za1v.q[w12], p1/m, z1.q
+mov za1v.q[w12, 0], p1/m, z1.q
+// CHECK-INST: mov za1v.q[w12, 0], p1/m, z1.q
// CHECK-ENCODING: [0x21,0x84,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 c1 c0 <unknown>
-mov za8v.q[w14], p5/m, z19.q
-// CHECK-INST: mov za8v.q[w14], p5/m, z19.q
+mov za8v.q[w14, 0], p5/m, z19.q
+// CHECK-INST: mov za8v.q[w14, 0], p5/m, z19.q
// CHECK-ENCODING: [0x68,0xd6,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 c1 c0 <unknown>
-mov za0v.q[w12], p6/m, z12.q
-// CHECK-INST: mov za0v.q[w12], p6/m, z12.q
+mov za0v.q[w12, 0], p6/m, z12.q
+// CHECK-INST: mov za0v.q[w12, 0], p6/m, z12.q
// CHECK-ENCODING: [0x80,0x99,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 c1 c0 <unknown>
-mov za1v.q[w14], p2/m, z1.q
-// CHECK-INST: mov za1v.q[w14], p2/m, z1.q
+mov za1v.q[w14, 0], p2/m, z1.q
+// CHECK-INST: mov za1v.q[w14, 0], p2/m, z1.q
// CHECK-ENCODING: [0x21,0xc8,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 c1 c0 <unknown>
-mov za13v.q[w12], p2/m, z22.q
-// CHECK-INST: mov za13v.q[w12], p2/m, z22.q
+mov za13v.q[w12, 0], p2/m, z22.q
+// CHECK-INST: mov za13v.q[w12, 0], p2/m, z22.q
// CHECK-ENCODING: [0xcd,0x8a,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a c1 c0 <unknown>
-mov za2v.q[w15], p5/m, z9.q
-// CHECK-INST: mov za2v.q[w15], p5/m, z9.q
+mov za2v.q[w15, 0], p5/m, z9.q
+// CHECK-INST: mov za2v.q[w15, 0], p5/m, z9.q
// CHECK-ENCODING: [0x22,0xf5,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 c1 c0 <unknown>
-mov za7v.q[w13], p2/m, z12.q
-// CHECK-INST: mov za7v.q[w13], p2/m, z12.q
+mov za7v.q[w13, 0], p2/m, z12.q
+// CHECK-INST: mov za7v.q[w13, 0], p2/m, z12.q
// CHECK-ENCODING: [0x87,0xa9,0xc1,0xc0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 c1 c0 <unknown>
diff --git a/llvm/test/MC/AArch64/SME/st1b-diagnostics.s b/llvm/test/MC/AArch64/SME/st1b-diagnostics.s
index 12f168ef7e46a..05ac2301041ff 100644
--- a/llvm/test/MC/AArch64/SME/st1b-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/st1b-diagnostics.s
@@ -3,32 +3,32 @@
// ------------------------------------------------------------------------- //
// Invalid tile (expected: za0h.b or za0v.b)
-st1b {za1h.b[w12, #0]}, p0, [x0]
+st1b {za1h.b[w12, 0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: st1b {za1h.b[w12, #0]}, p0, [x0]
+// CHECK-NEXT: st1b {za1h.b[w12, 0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1b {za[w12, #0]}, p0/z, [x0]
+st1b {za[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za0h.b or za0v.b
-// CHECK-NEXT: st1b {za[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: st1b {za[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1b {za15v.q[w12, #0]}, p0/z, [x0]
+st1b {za15v.q[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za0h.b or za0v.b
-// CHECK-NEXT: st1b {za15v.q[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: st1b {za15v.q[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid vector select register (expected: w12-w15)
-st1b {za0h.b[w11, #0]}, p0, [x0]
+st1b {za0h.b[w11, 0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: st1b {za0h.b[w11, #0]}, p0, [x0]
+// CHECK-NEXT: st1b {za0h.b[w11, 0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1b {za0h.b[w16, #0]}, p0, [x0]
+st1b {za0h.b[w16, 0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: st1b {za0h.b[w16, #0]}, p0, [x0]
+// CHECK-NEXT: st1b {za0h.b[w16, 0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
@@ -39,46 +39,46 @@ st1b {za0h.b[w12]}, p0, [x0]
// CHECK-NEXT: st1b {za0h.b[w12]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1b {za0h.b[w12, #16]}, p0, [x0]
+st1b {za0h.b[w12, 16]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
-// CHECK-NEXT: st1b {za0h.b[w12, #16]}, p0, [x0]
+// CHECK-NEXT: st1b {za0h.b[w12, 16]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate (expected: p0-p7)
-st1b {za0h.b[w12, #0]}, p8, [x0]
+st1b {za0h.b[w12, 0]}, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
-// CHECK-NEXT: st1b {za0h.b[w12, #0]}, p8, [x0]
+// CHECK-NEXT: st1b {za0h.b[w12, 0]}, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Unexpected predicate qualifier
-st1b {za0h.b[w12, #0]}, p0/z, [x0]
+st1b {za0h.b[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: st1b {za0h.b[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: st1b {za0h.b[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1b {za0h.b[w12, #0]}, p0/m, [x0]
+st1b {za0h.b[w12, 0]}, p0/m, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: st1b {za0h.b[w12, #0]}, p0/m, [x0]
+// CHECK-NEXT: st1b {za0h.b[w12, 0]}, p0/m, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid memory operands
-st1b {za0h.b[w12, #0]}, p0, [w0]
+st1b {za0h.b[w12, 0]}, p0, [w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: st1b {za0h.b[w12, #0]}, p0, [w0]
+// CHECK-NEXT: st1b {za0h.b[w12, 0]}, p0, [w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1b {za0h.b[w12, #0]}, p0, [x0, w0]
+st1b {za0h.b[w12, 0]}, p0, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
-// CHECK-NEXT: st1b {za0h.b[w12, #0]}, p0, [x0, w0]
+// CHECK-NEXT: st1b {za0h.b[w12, 0]}, p0, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1b {za0h.b[w12, #0]}, p0, [x0, x0, lsl #1]
+st1b {za0h.b[w12, 0]}, p0, [x0, x0, lsl #1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
-// CHECK-NEXT: st1b {za0h.b[w12, #0]}, p0, [x0, x0, lsl #1]
+// CHECK-NEXT: st1b {za0h.b[w12, 0]}, p0, [x0, x0, lsl #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/st1b.s b/llvm/test/MC/AArch64/SME/st1b.s
index 7c6e5fd7ba7fe..f13abb27cf7af 100644
--- a/llvm/test/MC/AArch64/SME/st1b.s
+++ b/llvm/test/MC/AArch64/SME/st1b.s
@@ -15,146 +15,146 @@
// --------------------------------------------------------------------------//
// Horizontal
-st1b {za0h.b[w12, #0]}, p0, [x0, x0]
-// CHECK-INST: st1b {za0h.b[w12, #0]}, p0, [x0, x0]
+st1b {za0h.b[w12, 0]}, p0, [x0, x0]
+// CHECK-INST: st1b {za0h.b[w12, 0]}, p0, [x0, x0]
// CHECK-ENCODING: [0x00,0x00,0x20,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 20 e0 <unknown>
-st1b {za0h.b[w14, #5]}, p5, [x10, x21]
-// CHECK-INST: st1b {za0h.b[w14, #5]}, p5, [x10, x21]
+st1b {za0h.b[w14, 5]}, p5, [x10, x21]
+// CHECK-INST: st1b {za0h.b[w14, 5]}, p5, [x10, x21]
// CHECK-ENCODING: [0x45,0x55,0x35,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 35 e0 <unknown>
-st1b {za0h.b[w15, #7]}, p3, [x13, x8]
-// CHECK-INST: st1b {za0h.b[w15, #7]}, p3, [x13, x8]
+st1b {za0h.b[w15, 7]}, p3, [x13, x8]
+// CHECK-INST: st1b {za0h.b[w15, 7]}, p3, [x13, x8]
// CHECK-ENCODING: [0xa7,0x6d,0x28,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 28 e0 <unknown>
-st1b {za0h.b[w15, #15]}, p7, [sp]
-// CHECK-INST: st1b {za0h.b[w15, #15]}, p7, [sp]
+st1b {za0h.b[w15, 15]}, p7, [sp]
+// CHECK-INST: st1b {za0h.b[w15, 15]}, p7, [sp]
// CHECK-ENCODING: [0xef,0x7f,0x3f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 3f e0 <unknown>
-st1b {za0h.b[w12, #5]}, p3, [x17, x16]
-// CHECK-INST: st1b {za0h.b[w12, #5]}, p3, [x17, x16]
+st1b {za0h.b[w12, 5]}, p3, [x17, x16]
+// CHECK-INST: st1b {za0h.b[w12, 5]}, p3, [x17, x16]
// CHECK-ENCODING: [0x25,0x0e,0x30,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 30 e0 <unknown>
-st1b {za0h.b[w12, #1]}, p1, [x1, x30]
-// CHECK-INST: st1b {za0h.b[w12, #1]}, p1, [x1, x30]
+st1b {za0h.b[w12, 1]}, p1, [x1, x30]
+// CHECK-INST: st1b {za0h.b[w12, 1]}, p1, [x1, x30]
// CHECK-ENCODING: [0x21,0x04,0x3e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 3e e0 <unknown>
-st1b {za0h.b[w14, #8]}, p5, [x19, x20]
-// CHECK-INST: st1b {za0h.b[w14, #8]}, p5, [x19, x20]
+st1b {za0h.b[w14, 8]}, p5, [x19, x20]
+// CHECK-INST: st1b {za0h.b[w14, 8]}, p5, [x19, x20]
// CHECK-ENCODING: [0x68,0x56,0x34,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 34 e0 <unknown>
-st1b {za0h.b[w12, #0]}, p6, [x12, x2]
-// CHECK-INST: st1b {za0h.b[w12, #0]}, p6, [x12, x2]
+st1b {za0h.b[w12, 0]}, p6, [x12, x2]
+// CHECK-INST: st1b {za0h.b[w12, 0]}, p6, [x12, x2]
// CHECK-ENCODING: [0x80,0x19,0x22,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 22 e0 <unknown>
-st1b {za0h.b[w14, #1]}, p2, [x1, x26]
-// CHECK-INST: st1b {za0h.b[w14, #1]}, p2, [x1, x26]
+st1b {za0h.b[w14, 1]}, p2, [x1, x26]
+// CHECK-INST: st1b {za0h.b[w14, 1]}, p2, [x1, x26]
// CHECK-ENCODING: [0x21,0x48,0x3a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 3a e0 <unknown>
-st1b {za0h.b[w12, #13]}, p2, [x22, x30]
-// CHECK-INST: st1b {za0h.b[w12, #13]}, p2, [x22, x30]
+st1b {za0h.b[w12, 13]}, p2, [x22, x30]
+// CHECK-INST: st1b {za0h.b[w12, 13]}, p2, [x22, x30]
// CHECK-ENCODING: [0xcd,0x0a,0x3e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 3e e0 <unknown>
-st1b {za0h.b[w15, #2]}, p5, [x9, x1]
-// CHECK-INST: st1b {za0h.b[w15, #2]}, p5, [x9, x1]
+st1b {za0h.b[w15, 2]}, p5, [x9, x1]
+// CHECK-INST: st1b {za0h.b[w15, 2]}, p5, [x9, x1]
// CHECK-ENCODING: [0x22,0x75,0x21,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 21 e0 <unknown>
-st1b {za0h.b[w13, #7]}, p2, [x12, x11]
-// CHECK-INST: st1b {za0h.b[w13, #7]}, p2, [x12, x11]
+st1b {za0h.b[w13, 7]}, p2, [x12, x11]
+// CHECK-INST: st1b {za0h.b[w13, 7]}, p2, [x12, x11]
// CHECK-ENCODING: [0x87,0x29,0x2b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 2b e0 <unknown>
-st1b za0h.b[w12, #0], p0, [x0, x0]
-// CHECK-INST: st1b {za0h.b[w12, #0]}, p0, [x0, x0]
+st1b za0h.b[w12, 0], p0, [x0, x0]
+// CHECK-INST: st1b {za0h.b[w12, 0]}, p0, [x0, x0]
// CHECK-ENCODING: [0x00,0x00,0x20,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 20 e0 <unknown>
-st1b za0h.b[w14, #5], p5, [x10, x21]
-// CHECK-INST: st1b {za0h.b[w14, #5]}, p5, [x10, x21]
+st1b za0h.b[w14, 5], p5, [x10, x21]
+// CHECK-INST: st1b {za0h.b[w14, 5]}, p5, [x10, x21]
// CHECK-ENCODING: [0x45,0x55,0x35,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 35 e0 <unknown>
-st1b za0h.b[w15, #7], p3, [x13, x8]
-// CHECK-INST: st1b {za0h.b[w15, #7]}, p3, [x13, x8]
+st1b za0h.b[w15, 7], p3, [x13, x8]
+// CHECK-INST: st1b {za0h.b[w15, 7]}, p3, [x13, x8]
// CHECK-ENCODING: [0xa7,0x6d,0x28,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 28 e0 <unknown>
-st1b za0h.b[w15, #15], p7, [sp]
-// CHECK-INST: st1b {za0h.b[w15, #15]}, p7, [sp]
+st1b za0h.b[w15, 15], p7, [sp]
+// CHECK-INST: st1b {za0h.b[w15, 15]}, p7, [sp]
// CHECK-ENCODING: [0xef,0x7f,0x3f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 3f e0 <unknown>
-st1b za0h.b[w12, #5], p3, [x17, x16]
-// CHECK-INST: st1b {za0h.b[w12, #5]}, p3, [x17, x16]
+st1b za0h.b[w12, 5], p3, [x17, x16]
+// CHECK-INST: st1b {za0h.b[w12, 5]}, p3, [x17, x16]
// CHECK-ENCODING: [0x25,0x0e,0x30,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 30 e0 <unknown>
-st1b za0h.b[w12, #1], p1, [x1, x30]
-// CHECK-INST: st1b {za0h.b[w12, #1]}, p1, [x1, x30]
+st1b za0h.b[w12, 1], p1, [x1, x30]
+// CHECK-INST: st1b {za0h.b[w12, 1]}, p1, [x1, x30]
// CHECK-ENCODING: [0x21,0x04,0x3e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 3e e0 <unknown>
-st1b za0h.b[w14, #8], p5, [x19, x20]
-// CHECK-INST: st1b {za0h.b[w14, #8]}, p5, [x19, x20]
+st1b za0h.b[w14, 8], p5, [x19, x20]
+// CHECK-INST: st1b {za0h.b[w14, 8]}, p5, [x19, x20]
// CHECK-ENCODING: [0x68,0x56,0x34,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 34 e0 <unknown>
-st1b za0h.b[w12, #0], p6, [x12, x2]
-// CHECK-INST: st1b {za0h.b[w12, #0]}, p6, [x12, x2]
+st1b za0h.b[w12, 0], p6, [x12, x2]
+// CHECK-INST: st1b {za0h.b[w12, 0]}, p6, [x12, x2]
// CHECK-ENCODING: [0x80,0x19,0x22,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 22 e0 <unknown>
-st1b za0h.b[w14, #1], p2, [x1, x26]
-// CHECK-INST: st1b {za0h.b[w14, #1]}, p2, [x1, x26]
+st1b za0h.b[w14, 1], p2, [x1, x26]
+// CHECK-INST: st1b {za0h.b[w14, 1]}, p2, [x1, x26]
// CHECK-ENCODING: [0x21,0x48,0x3a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 3a e0 <unknown>
-st1b za0h.b[w12, #13], p2, [x22, x30]
-// CHECK-INST: st1b {za0h.b[w12, #13]}, p2, [x22, x30]
+st1b za0h.b[w12, 13], p2, [x22, x30]
+// CHECK-INST: st1b {za0h.b[w12, 13]}, p2, [x22, x30]
// CHECK-ENCODING: [0xcd,0x0a,0x3e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 3e e0 <unknown>
-st1b za0h.b[w15, #2], p5, [x9, x1]
-// CHECK-INST: st1b {za0h.b[w15, #2]}, p5, [x9, x1]
+st1b za0h.b[w15, 2], p5, [x9, x1]
+// CHECK-INST: st1b {za0h.b[w15, 2]}, p5, [x9, x1]
// CHECK-ENCODING: [0x22,0x75,0x21,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 21 e0 <unknown>
-st1b za0h.b[w13, #7], p2, [x12, x11]
-// CHECK-INST: st1b {za0h.b[w13, #7]}, p2, [x12, x11]
+st1b za0h.b[w13, 7], p2, [x12, x11]
+// CHECK-INST: st1b {za0h.b[w13, 7]}, p2, [x12, x11]
// CHECK-ENCODING: [0x87,0x29,0x2b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 2b e0 <unknown>
@@ -162,146 +162,146 @@ st1b za0h.b[w13, #7], p2, [x12, x11]
// --------------------------------------------------------------------------//
// Vertical
-st1b {za0v.b[w12, #0]}, p0, [x0, x0]
-// CHECK-INST: st1b {za0v.b[w12, #0]}, p0, [x0, x0]
+st1b {za0v.b[w12, 0]}, p0, [x0, x0]
+// CHECK-INST: st1b {za0v.b[w12, 0]}, p0, [x0, x0]
// CHECK-ENCODING: [0x00,0x80,0x20,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 20 e0 <unknown>
-st1b {za0v.b[w14, #5]}, p5, [x10, x21]
-// CHECK-INST: st1b {za0v.b[w14, #5]}, p5, [x10, x21]
+st1b {za0v.b[w14, 5]}, p5, [x10, x21]
+// CHECK-INST: st1b {za0v.b[w14, 5]}, p5, [x10, x21]
// CHECK-ENCODING: [0x45,0xd5,0x35,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 35 e0 <unknown>
-st1b {za0v.b[w15, #7]}, p3, [x13, x8]
-// CHECK-INST: st1b {za0v.b[w15, #7]}, p3, [x13, x8]
+st1b {za0v.b[w15, 7]}, p3, [x13, x8]
+// CHECK-INST: st1b {za0v.b[w15, 7]}, p3, [x13, x8]
// CHECK-ENCODING: [0xa7,0xed,0x28,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 28 e0 <unknown>
-st1b {za0v.b[w15, #15]}, p7, [sp]
-// CHECK-INST: st1b {za0v.b[w15, #15]}, p7, [sp]
+st1b {za0v.b[w15, 15]}, p7, [sp]
+// CHECK-INST: st1b {za0v.b[w15, 15]}, p7, [sp]
// CHECK-ENCODING: [0xef,0xff,0x3f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 3f e0 <unknown>
-st1b {za0v.b[w12, #5]}, p3, [x17, x16]
-// CHECK-INST: st1b {za0v.b[w12, #5]}, p3, [x17, x16]
+st1b {za0v.b[w12, 5]}, p3, [x17, x16]
+// CHECK-INST: st1b {za0v.b[w12, 5]}, p3, [x17, x16]
// CHECK-ENCODING: [0x25,0x8e,0x30,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 30 e0 <unknown>
-st1b {za0v.b[w12, #1]}, p1, [x1, x30]
-// CHECK-INST: st1b {za0v.b[w12, #1]}, p1, [x1, x30]
+st1b {za0v.b[w12, 1]}, p1, [x1, x30]
+// CHECK-INST: st1b {za0v.b[w12, 1]}, p1, [x1, x30]
// CHECK-ENCODING: [0x21,0x84,0x3e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 3e e0 <unknown>
-st1b {za0v.b[w14, #8]}, p5, [x19, x20]
-// CHECK-INST: st1b {za0v.b[w14, #8]}, p5, [x19, x20]
+st1b {za0v.b[w14, 8]}, p5, [x19, x20]
+// CHECK-INST: st1b {za0v.b[w14, 8]}, p5, [x19, x20]
// CHECK-ENCODING: [0x68,0xd6,0x34,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 34 e0 <unknown>
-st1b {za0v.b[w12, #0]}, p6, [x12, x2]
-// CHECK-INST: st1b {za0v.b[w12, #0]}, p6, [x12, x2]
+st1b {za0v.b[w12, 0]}, p6, [x12, x2]
+// CHECK-INST: st1b {za0v.b[w12, 0]}, p6, [x12, x2]
// CHECK-ENCODING: [0x80,0x99,0x22,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 22 e0 <unknown>
-st1b {za0v.b[w14, #1]}, p2, [x1, x26]
-// CHECK-INST: st1b {za0v.b[w14, #1]}, p2, [x1, x26]
+st1b {za0v.b[w14, 1]}, p2, [x1, x26]
+// CHECK-INST: st1b {za0v.b[w14, 1]}, p2, [x1, x26]
// CHECK-ENCODING: [0x21,0xc8,0x3a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 3a e0 <unknown>
-st1b {za0v.b[w12, #13]}, p2, [x22, x30]
-// CHECK-INST: st1b {za0v.b[w12, #13]}, p2, [x22, x30]
+st1b {za0v.b[w12, 13]}, p2, [x22, x30]
+// CHECK-INST: st1b {za0v.b[w12, 13]}, p2, [x22, x30]
// CHECK-ENCODING: [0xcd,0x8a,0x3e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 3e e0 <unknown>
-st1b {za0v.b[w15, #2]}, p5, [x9, x1]
-// CHECK-INST: st1b {za0v.b[w15, #2]}, p5, [x9, x1]
+st1b {za0v.b[w15, 2]}, p5, [x9, x1]
+// CHECK-INST: st1b {za0v.b[w15, 2]}, p5, [x9, x1]
// CHECK-ENCODING: [0x22,0xf5,0x21,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 21 e0 <unknown>
-st1b {za0v.b[w13, #7]}, p2, [x12, x11]
-// CHECK-INST: st1b {za0v.b[w13, #7]}, p2, [x12, x11]
+st1b {za0v.b[w13, 7]}, p2, [x12, x11]
+// CHECK-INST: st1b {za0v.b[w13, 7]}, p2, [x12, x11]
// CHECK-ENCODING: [0x87,0xa9,0x2b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 2b e0 <unknown>
-st1b za0v.b[w12, #0], p0, [x0, x0]
-// CHECK-INST: st1b {za0v.b[w12, #0]}, p0, [x0, x0]
+st1b za0v.b[w12, 0], p0, [x0, x0]
+// CHECK-INST: st1b {za0v.b[w12, 0]}, p0, [x0, x0]
// CHECK-ENCODING: [0x00,0x80,0x20,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 20 e0 <unknown>
-st1b za0v.b[w14, #5], p5, [x10, x21]
-// CHECK-INST: st1b {za0v.b[w14, #5]}, p5, [x10, x21]
+st1b za0v.b[w14, 5], p5, [x10, x21]
+// CHECK-INST: st1b {za0v.b[w14, 5]}, p5, [x10, x21]
// CHECK-ENCODING: [0x45,0xd5,0x35,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 35 e0 <unknown>
-st1b za0v.b[w15, #7], p3, [x13, x8]
-// CHECK-INST: st1b {za0v.b[w15, #7]}, p3, [x13, x8]
+st1b za0v.b[w15, 7], p3, [x13, x8]
+// CHECK-INST: st1b {za0v.b[w15, 7]}, p3, [x13, x8]
// CHECK-ENCODING: [0xa7,0xed,0x28,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 28 e0 <unknown>
-st1b za0v.b[w15, #15], p7, [sp]
-// CHECK-INST: st1b {za0v.b[w15, #15]}, p7, [sp]
+st1b za0v.b[w15, 15], p7, [sp]
+// CHECK-INST: st1b {za0v.b[w15, 15]}, p7, [sp]
// CHECK-ENCODING: [0xef,0xff,0x3f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 3f e0 <unknown>
-st1b za0v.b[w12, #5], p3, [x17, x16]
-// CHECK-INST: st1b {za0v.b[w12, #5]}, p3, [x17, x16]
+st1b za0v.b[w12, 5], p3, [x17, x16]
+// CHECK-INST: st1b {za0v.b[w12, 5]}, p3, [x17, x16]
// CHECK-ENCODING: [0x25,0x8e,0x30,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 30 e0 <unknown>
-st1b za0v.b[w12, #1], p1, [x1, x30]
-// CHECK-INST: st1b {za0v.b[w12, #1]}, p1, [x1, x30]
+st1b za0v.b[w12, 1], p1, [x1, x30]
+// CHECK-INST: st1b {za0v.b[w12, 1]}, p1, [x1, x30]
// CHECK-ENCODING: [0x21,0x84,0x3e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 3e e0 <unknown>
-st1b za0v.b[w14, #8], p5, [x19, x20]
-// CHECK-INST: st1b {za0v.b[w14, #8]}, p5, [x19, x20]
+st1b za0v.b[w14, 8], p5, [x19, x20]
+// CHECK-INST: st1b {za0v.b[w14, 8]}, p5, [x19, x20]
// CHECK-ENCODING: [0x68,0xd6,0x34,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 34 e0 <unknown>
-st1b za0v.b[w12, #0], p6, [x12, x2]
-// CHECK-INST: st1b {za0v.b[w12, #0]}, p6, [x12, x2]
+st1b za0v.b[w12, 0], p6, [x12, x2]
+// CHECK-INST: st1b {za0v.b[w12, 0]}, p6, [x12, x2]
// CHECK-ENCODING: [0x80,0x99,0x22,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 22 e0 <unknown>
-st1b za0v.b[w14, #1], p2, [x1, x26]
-// CHECK-INST: st1b {za0v.b[w14, #1]}, p2, [x1, x26]
+st1b za0v.b[w14, 1], p2, [x1, x26]
+// CHECK-INST: st1b {za0v.b[w14, 1]}, p2, [x1, x26]
// CHECK-ENCODING: [0x21,0xc8,0x3a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 3a e0 <unknown>
-st1b za0v.b[w12, #13], p2, [x22, x30]
-// CHECK-INST: st1b {za0v.b[w12, #13]}, p2, [x22, x30]
+st1b za0v.b[w12, 13], p2, [x22, x30]
+// CHECK-INST: st1b {za0v.b[w12, 13]}, p2, [x22, x30]
// CHECK-ENCODING: [0xcd,0x8a,0x3e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 3e e0 <unknown>
-st1b za0v.b[w15, #2], p5, [x9, x1]
-// CHECK-INST: st1b {za0v.b[w15, #2]}, p5, [x9, x1]
+st1b za0v.b[w15, 2], p5, [x9, x1]
+// CHECK-INST: st1b {za0v.b[w15, 2]}, p5, [x9, x1]
// CHECK-ENCODING: [0x22,0xf5,0x21,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 21 e0 <unknown>
-st1b za0v.b[w13, #7], p2, [x12, x11]
-// CHECK-INST: st1b {za0v.b[w13, #7]}, p2, [x12, x11]
+st1b za0v.b[w13, 7], p2, [x12, x11]
+// CHECK-INST: st1b {za0v.b[w13, 7]}, p2, [x12, x11]
// CHECK-ENCODING: [0x87,0xa9,0x2b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 2b e0 <unknown>
diff --git a/llvm/test/MC/AArch64/SME/st1d-diagnostics.s b/llvm/test/MC/AArch64/SME/st1d-diagnostics.s
index 260275af8ff0e..ad6a5ab6f59cc 100644
--- a/llvm/test/MC/AArch64/SME/st1d-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/st1d-diagnostics.s
@@ -3,32 +3,32 @@
// ------------------------------------------------------------------------- //
// Invalid tile (expected: za[0-7]h.d or za[0-7]v.d)
-st1d {za8h.d[w12, #0]}, p0, [x0]
+st1d {za8h.d[w12, 0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: st1d {za8h.d[w12, #0]}, p0, [x0]
+// CHECK-NEXT: st1d {za8h.d[w12, 0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1d {za[w12, #0]}, p0/z, [x0]
+st1d {za[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-7]h.d or za[0-7]v.d
-// CHECK-NEXT: st1d {za[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: st1d {za[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1d {za3h.s[w12, #0]}, p0/z, [x0]
+st1d {za3h.s[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-7]h.d or za[0-7]v.d
-// CHECK-NEXT: st1d {za3h.s[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: st1d {za3h.s[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid vector select register (expected: w12-w15)
-st1d {za0h.d[w11, #0]}, p0, [x0]
+st1d {za0h.d[w11, 0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: st1d {za0h.d[w11, #0]}, p0, [x0]
+// CHECK-NEXT: st1d {za0h.d[w11, 0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1d {za0h.d[w16, #0]}, p0, [x0]
+st1d {za0h.d[w16, 0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: st1d {za0h.d[w16, #0]}, p0, [x0]
+// CHECK-NEXT: st1d {za0h.d[w16, 0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
@@ -39,46 +39,46 @@ st1d {za0h.d[w12]}, p0, [x0]
// CHECK-NEXT: st1d {za0h.d[w12]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1d {za0h.d[w12, #2]}, p0, [x0]
+st1d {za0h.d[w12, 2]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
-// CHECK-NEXT: st1d {za0h.d[w12, #2]}, p0, [x0]
+// CHECK-NEXT: st1d {za0h.d[w12, 2]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate (expected: p0-p7)
-st1d {za0h.d[w12, #0]}, p8, [x0]
+st1d {za0h.d[w12, 0]}, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
-// CHECK-NEXT: st1d {za0h.d[w12, #0]}, p8, [x0]
+// CHECK-NEXT: st1d {za0h.d[w12, 0]}, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Unexpected predicate qualifier
-st1d {za0h.d[w12, #0]}, p0/z, [x0]
+st1d {za0h.d[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: st1d {za0h.d[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: st1d {za0h.d[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1d {za0h.d[w12, #0]}, p0/m, [x0]
+st1d {za0h.d[w12, 0]}, p0/m, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: st1d {za0h.d[w12, #0]}, p0/m, [x0]
+// CHECK-NEXT: st1d {za0h.d[w12, 0]}, p0/m, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid memory operands
-st1d {za0h.d[w12, #0]}, p0, [w0]
+st1d {za0h.d[w12, 0]}, p0, [w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: st1d {za0h.d[w12, #0]}, p0, [w0]
+// CHECK-NEXT: st1d {za0h.d[w12, 0]}, p0, [w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1d {za0h.d[w12, #0]}, p0, [x0, w0]
+st1d {za0h.d[w12, 0]}, p0, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
-// CHECK-NEXT: st1d {za0h.d[w12, #0]}, p0, [x0, w0]
+// CHECK-NEXT: st1d {za0h.d[w12, 0]}, p0, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1d {za0h.d[w12, #0]}, p0, [x0, x0, lsl #4]
+st1d {za0h.d[w12, 0]}, p0, [x0, x0, lsl #4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
-// CHECK-NEXT: st1d {za0h.d[w12, #0]}, p0, [x0, x0, lsl #4]
+// CHECK-NEXT: st1d {za0h.d[w12, 0]}, p0, [x0, x0, lsl #4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/st1d.s b/llvm/test/MC/AArch64/SME/st1d.s
index b753efb1bdf0a..1c0ae83f8b051 100644
--- a/llvm/test/MC/AArch64/SME/st1d.s
+++ b/llvm/test/MC/AArch64/SME/st1d.s
@@ -15,146 +15,146 @@
// --------------------------------------------------------------------------//
// Horizontal
-st1d {za0h.d[w12, #0]}, p0, [x0, x0, lsl #3]
-// CHECK-INST: st1d {za0h.d[w12, #0]}, p0, [x0, x0, lsl #3]
+st1d {za0h.d[w12, 0]}, p0, [x0, x0, lsl #3]
+// CHECK-INST: st1d {za0h.d[w12, 0]}, p0, [x0, x0, lsl #3]
// CHECK-ENCODING: [0x00,0x00,0xe0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 e0 e0 <unknown>
-st1d {za2h.d[w14, #1]}, p5, [x10, x21, lsl #3]
-// CHECK-INST: st1d {za2h.d[w14, #1]}, p5, [x10, x21, lsl #3]
+st1d {za2h.d[w14, 1]}, p5, [x10, x21, lsl #3]
+// CHECK-INST: st1d {za2h.d[w14, 1]}, p5, [x10, x21, lsl #3]
// CHECK-ENCODING: [0x45,0x55,0xf5,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 f5 e0 <unknown>
-st1d {za3h.d[w15, #1]}, p3, [x13, x8, lsl #3]
-// CHECK-INST: st1d {za3h.d[w15, #1]}, p3, [x13, x8, lsl #3]
+st1d {za3h.d[w15, 1]}, p3, [x13, x8, lsl #3]
+// CHECK-INST: st1d {za3h.d[w15, 1]}, p3, [x13, x8, lsl #3]
// CHECK-ENCODING: [0xa7,0x6d,0xe8,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d e8 e0 <unknown>
-st1d {za7h.d[w15, #1]}, p7, [sp]
-// CHECK-INST: st1d {za7h.d[w15, #1]}, p7, [sp]
+st1d {za7h.d[w15, 1]}, p7, [sp]
+// CHECK-INST: st1d {za7h.d[w15, 1]}, p7, [sp]
// CHECK-ENCODING: [0xef,0x7f,0xff,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f ff e0 <unknown>
-st1d {za2h.d[w12, #1]}, p3, [x17, x16, lsl #3]
-// CHECK-INST: st1d {za2h.d[w12, #1]}, p3, [x17, x16, lsl #3]
+st1d {za2h.d[w12, 1]}, p3, [x17, x16, lsl #3]
+// CHECK-INST: st1d {za2h.d[w12, 1]}, p3, [x17, x16, lsl #3]
// CHECK-ENCODING: [0x25,0x0e,0xf0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e f0 e0 <unknown>
-st1d {za0h.d[w12, #1]}, p1, [x1, x30, lsl #3]
-// CHECK-INST: st1d {za0h.d[w12, #1]}, p1, [x1, x30, lsl #3]
+st1d {za0h.d[w12, 1]}, p1, [x1, x30, lsl #3]
+// CHECK-INST: st1d {za0h.d[w12, 1]}, p1, [x1, x30, lsl #3]
// CHECK-ENCODING: [0x21,0x04,0xfe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 fe e0 <unknown>
-st1d {za4h.d[w14, #0]}, p5, [x19, x20, lsl #3]
-// CHECK-INST: st1d {za4h.d[w14, #0]}, p5, [x19, x20, lsl #3]
+st1d {za4h.d[w14, 0]}, p5, [x19, x20, lsl #3]
+// CHECK-INST: st1d {za4h.d[w14, 0]}, p5, [x19, x20, lsl #3]
// CHECK-ENCODING: [0x68,0x56,0xf4,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 f4 e0 <unknown>
-st1d {za0h.d[w12, #0]}, p6, [x12, x2, lsl #3]
-// CHECK-INST: st1d {za0h.d[w12, #0]}, p6, [x12, x2, lsl #3]
+st1d {za0h.d[w12, 0]}, p6, [x12, x2, lsl #3]
+// CHECK-INST: st1d {za0h.d[w12, 0]}, p6, [x12, x2, lsl #3]
// CHECK-ENCODING: [0x80,0x19,0xe2,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 e2 e0 <unknown>
-st1d {za0h.d[w14, #1]}, p2, [x1, x26, lsl #3]
-// CHECK-INST: st1d {za0h.d[w14, #1]}, p2, [x1, x26, lsl #3]
+st1d {za0h.d[w14, 1]}, p2, [x1, x26, lsl #3]
+// CHECK-INST: st1d {za0h.d[w14, 1]}, p2, [x1, x26, lsl #3]
// CHECK-ENCODING: [0x21,0x48,0xfa,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 fa e0 <unknown>
-st1d {za6h.d[w12, #1]}, p2, [x22, x30, lsl #3]
-// CHECK-INST: st1d {za6h.d[w12, #1]}, p2, [x22, x30, lsl #3]
+st1d {za6h.d[w12, 1]}, p2, [x22, x30, lsl #3]
+// CHECK-INST: st1d {za6h.d[w12, 1]}, p2, [x22, x30, lsl #3]
// CHECK-ENCODING: [0xcd,0x0a,0xfe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a fe e0 <unknown>
-st1d {za1h.d[w15, #0]}, p5, [x9, x1, lsl #3]
-// CHECK-INST: st1d {za1h.d[w15, #0]}, p5, [x9, x1, lsl #3]
+st1d {za1h.d[w15, 0]}, p5, [x9, x1, lsl #3]
+// CHECK-INST: st1d {za1h.d[w15, 0]}, p5, [x9, x1, lsl #3]
// CHECK-ENCODING: [0x22,0x75,0xe1,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 e1 e0 <unknown>
-st1d {za3h.d[w13, #1]}, p2, [x12, x11, lsl #3]
-// CHECK-INST: st1d {za3h.d[w13, #1]}, p2, [x12, x11, lsl #3]
+st1d {za3h.d[w13, 1]}, p2, [x12, x11, lsl #3]
+// CHECK-INST: st1d {za3h.d[w13, 1]}, p2, [x12, x11, lsl #3]
// CHECK-ENCODING: [0x87,0x29,0xeb,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 eb e0 <unknown>
-st1d za0h.d[w12, #0], p0, [x0, x0, lsl #3]
-// CHECK-INST: st1d {za0h.d[w12, #0]}, p0, [x0, x0, lsl #3]
+st1d za0h.d[w12, 0], p0, [x0, x0, lsl #3]
+// CHECK-INST: st1d {za0h.d[w12, 0]}, p0, [x0, x0, lsl #3]
// CHECK-ENCODING: [0x00,0x00,0xe0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 e0 e0 <unknown>
-st1d za2h.d[w14, #1], p5, [x10, x21, lsl #3]
-// CHECK-INST: st1d {za2h.d[w14, #1]}, p5, [x10, x21, lsl #3]
+st1d za2h.d[w14, 1], p5, [x10, x21, lsl #3]
+// CHECK-INST: st1d {za2h.d[w14, 1]}, p5, [x10, x21, lsl #3]
// CHECK-ENCODING: [0x45,0x55,0xf5,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 f5 e0 <unknown>
-st1d za3h.d[w15, #1], p3, [x13, x8, lsl #3]
-// CHECK-INST: st1d {za3h.d[w15, #1]}, p3, [x13, x8, lsl #3]
+st1d za3h.d[w15, 1], p3, [x13, x8, lsl #3]
+// CHECK-INST: st1d {za3h.d[w15, 1]}, p3, [x13, x8, lsl #3]
// CHECK-ENCODING: [0xa7,0x6d,0xe8,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d e8 e0 <unknown>
-st1d za7h.d[w15, #1], p7, [sp]
-// CHECK-INST: st1d {za7h.d[w15, #1]}, p7, [sp]
+st1d za7h.d[w15, 1], p7, [sp]
+// CHECK-INST: st1d {za7h.d[w15, 1]}, p7, [sp]
// CHECK-ENCODING: [0xef,0x7f,0xff,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f ff e0 <unknown>
-st1d za2h.d[w12, #1], p3, [x17, x16, lsl #3]
-// CHECK-INST: st1d {za2h.d[w12, #1]}, p3, [x17, x16, lsl #3]
+st1d za2h.d[w12, 1], p3, [x17, x16, lsl #3]
+// CHECK-INST: st1d {za2h.d[w12, 1]}, p3, [x17, x16, lsl #3]
// CHECK-ENCODING: [0x25,0x0e,0xf0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e f0 e0 <unknown>
-st1d za0h.d[w12, #1], p1, [x1, x30, lsl #3]
-// CHECK-INST: st1d {za0h.d[w12, #1]}, p1, [x1, x30, lsl #3]
+st1d za0h.d[w12, 1], p1, [x1, x30, lsl #3]
+// CHECK-INST: st1d {za0h.d[w12, 1]}, p1, [x1, x30, lsl #3]
// CHECK-ENCODING: [0x21,0x04,0xfe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 fe e0 <unknown>
-st1d za4h.d[w14, #0], p5, [x19, x20, lsl #3]
-// CHECK-INST: st1d {za4h.d[w14, #0]}, p5, [x19, x20, lsl #3]
+st1d za4h.d[w14, 0], p5, [x19, x20, lsl #3]
+// CHECK-INST: st1d {za4h.d[w14, 0]}, p5, [x19, x20, lsl #3]
// CHECK-ENCODING: [0x68,0x56,0xf4,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 f4 e0 <unknown>
-st1d za0h.d[w12, #0], p6, [x12, x2, lsl #3]
-// CHECK-INST: st1d {za0h.d[w12, #0]}, p6, [x12, x2, lsl #3]
+st1d za0h.d[w12, 0], p6, [x12, x2, lsl #3]
+// CHECK-INST: st1d {za0h.d[w12, 0]}, p6, [x12, x2, lsl #3]
// CHECK-ENCODING: [0x80,0x19,0xe2,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 e2 e0 <unknown>
-st1d za0h.d[w14, #1], p2, [x1, x26, lsl #3]
-// CHECK-INST: st1d {za0h.d[w14, #1]}, p2, [x1, x26, lsl #3]
+st1d za0h.d[w14, 1], p2, [x1, x26, lsl #3]
+// CHECK-INST: st1d {za0h.d[w14, 1]}, p2, [x1, x26, lsl #3]
// CHECK-ENCODING: [0x21,0x48,0xfa,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 fa e0 <unknown>
-st1d za6h.d[w12, #1], p2, [x22, x30, lsl #3]
-// CHECK-INST: st1d {za6h.d[w12, #1]}, p2, [x22, x30, lsl #3]
+st1d za6h.d[w12, 1], p2, [x22, x30, lsl #3]
+// CHECK-INST: st1d {za6h.d[w12, 1]}, p2, [x22, x30, lsl #3]
// CHECK-ENCODING: [0xcd,0x0a,0xfe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a fe e0 <unknown>
-st1d za1h.d[w15, #0], p5, [x9, x1, lsl #3]
-// CHECK-INST: st1d {za1h.d[w15, #0]}, p5, [x9, x1, lsl #3]
+st1d za1h.d[w15, 0], p5, [x9, x1, lsl #3]
+// CHECK-INST: st1d {za1h.d[w15, 0]}, p5, [x9, x1, lsl #3]
// CHECK-ENCODING: [0x22,0x75,0xe1,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 e1 e0 <unknown>
-st1d za3h.d[w13, #1], p2, [x12, x11, lsl #3]
-// CHECK-INST: st1d {za3h.d[w13, #1]}, p2, [x12, x11, lsl #3]
+st1d za3h.d[w13, 1], p2, [x12, x11, lsl #3]
+// CHECK-INST: st1d {za3h.d[w13, 1]}, p2, [x12, x11, lsl #3]
// CHECK-ENCODING: [0x87,0x29,0xeb,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 eb e0 <unknown>
@@ -162,146 +162,146 @@ st1d za3h.d[w13, #1], p2, [x12, x11, lsl #3]
// --------------------------------------------------------------------------//
// Vertical
-st1d {za0v.d[w12, #0]}, p0, [x0, x0, lsl #3]
-// CHECK-INST: st1d {za0v.d[w12, #0]}, p0, [x0, x0, lsl #3]
+st1d {za0v.d[w12, 0]}, p0, [x0, x0, lsl #3]
+// CHECK-INST: st1d {za0v.d[w12, 0]}, p0, [x0, x0, lsl #3]
// CHECK-ENCODING: [0x00,0x80,0xe0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 e0 e0 <unknown>
-st1d {za2v.d[w14, #1]}, p5, [x10, x21, lsl #3]
-// CHECK-INST: st1d {za2v.d[w14, #1]}, p5, [x10, x21, lsl #3]
+st1d {za2v.d[w14, 1]}, p5, [x10, x21, lsl #3]
+// CHECK-INST: st1d {za2v.d[w14, 1]}, p5, [x10, x21, lsl #3]
// CHECK-ENCODING: [0x45,0xd5,0xf5,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 f5 e0 <unknown>
-st1d {za3v.d[w15, #1]}, p3, [x13, x8, lsl #3]
-// CHECK-INST: st1d {za3v.d[w15, #1]}, p3, [x13, x8, lsl #3]
+st1d {za3v.d[w15, 1]}, p3, [x13, x8, lsl #3]
+// CHECK-INST: st1d {za3v.d[w15, 1]}, p3, [x13, x8, lsl #3]
// CHECK-ENCODING: [0xa7,0xed,0xe8,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed e8 e0 <unknown>
-st1d {za7v.d[w15, #1]}, p7, [sp]
-// CHECK-INST: st1d {za7v.d[w15, #1]}, p7, [sp]
+st1d {za7v.d[w15, 1]}, p7, [sp]
+// CHECK-INST: st1d {za7v.d[w15, 1]}, p7, [sp]
// CHECK-ENCODING: [0xef,0xff,0xff,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff ff e0 <unknown>
-st1d {za2v.d[w12, #1]}, p3, [x17, x16, lsl #3]
-// CHECK-INST: st1d {za2v.d[w12, #1]}, p3, [x17, x16, lsl #3]
+st1d {za2v.d[w12, 1]}, p3, [x17, x16, lsl #3]
+// CHECK-INST: st1d {za2v.d[w12, 1]}, p3, [x17, x16, lsl #3]
// CHECK-ENCODING: [0x25,0x8e,0xf0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e f0 e0 <unknown>
-st1d {za0v.d[w12, #1]}, p1, [x1, x30, lsl #3]
-// CHECK-INST: st1d {za0v.d[w12, #1]}, p1, [x1, x30, lsl #3]
+st1d {za0v.d[w12, 1]}, p1, [x1, x30, lsl #3]
+// CHECK-INST: st1d {za0v.d[w12, 1]}, p1, [x1, x30, lsl #3]
// CHECK-ENCODING: [0x21,0x84,0xfe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 fe e0 <unknown>
-st1d {za4v.d[w14, #0]}, p5, [x19, x20, lsl #3]
-// CHECK-INST: st1d {za4v.d[w14, #0]}, p5, [x19, x20, lsl #3]
+st1d {za4v.d[w14, 0]}, p5, [x19, x20, lsl #3]
+// CHECK-INST: st1d {za4v.d[w14, 0]}, p5, [x19, x20, lsl #3]
// CHECK-ENCODING: [0x68,0xd6,0xf4,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 f4 e0 <unknown>
-st1d {za0v.d[w12, #0]}, p6, [x12, x2, lsl #3]
-// CHECK-INST: st1d {za0v.d[w12, #0]}, p6, [x12, x2, lsl #3]
+st1d {za0v.d[w12, 0]}, p6, [x12, x2, lsl #3]
+// CHECK-INST: st1d {za0v.d[w12, 0]}, p6, [x12, x2, lsl #3]
// CHECK-ENCODING: [0x80,0x99,0xe2,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 e2 e0 <unknown>
-st1d {za0v.d[w14, #1]}, p2, [x1, x26, lsl #3]
-// CHECK-INST: st1d {za0v.d[w14, #1]}, p2, [x1, x26, lsl #3]
+st1d {za0v.d[w14, 1]}, p2, [x1, x26, lsl #3]
+// CHECK-INST: st1d {za0v.d[w14, 1]}, p2, [x1, x26, lsl #3]
// CHECK-ENCODING: [0x21,0xc8,0xfa,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 fa e0 <unknown>
-st1d {za6v.d[w12, #1]}, p2, [x22, x30, lsl #3]
-// CHECK-INST: st1d {za6v.d[w12, #1]}, p2, [x22, x30, lsl #3]
+st1d {za6v.d[w12, 1]}, p2, [x22, x30, lsl #3]
+// CHECK-INST: st1d {za6v.d[w12, 1]}, p2, [x22, x30, lsl #3]
// CHECK-ENCODING: [0xcd,0x8a,0xfe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a fe e0 <unknown>
-st1d {za1v.d[w15, #0]}, p5, [x9, x1, lsl #3]
-// CHECK-INST: st1d {za1v.d[w15, #0]}, p5, [x9, x1, lsl #3]
+st1d {za1v.d[w15, 0]}, p5, [x9, x1, lsl #3]
+// CHECK-INST: st1d {za1v.d[w15, 0]}, p5, [x9, x1, lsl #3]
// CHECK-ENCODING: [0x22,0xf5,0xe1,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 e1 e0 <unknown>
-st1d {za3v.d[w13, #1]}, p2, [x12, x11, lsl #3]
-// CHECK-INST: st1d {za3v.d[w13, #1]}, p2, [x12, x11, lsl #3]
+st1d {za3v.d[w13, 1]}, p2, [x12, x11, lsl #3]
+// CHECK-INST: st1d {za3v.d[w13, 1]}, p2, [x12, x11, lsl #3]
// CHECK-ENCODING: [0x87,0xa9,0xeb,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 eb e0 <unknown>
-st1d za0v.d[w12, #0], p0, [x0, x0, lsl #3]
-// CHECK-INST: st1d {za0v.d[w12, #0]}, p0, [x0, x0, lsl #3]
+st1d za0v.d[w12, 0], p0, [x0, x0, lsl #3]
+// CHECK-INST: st1d {za0v.d[w12, 0]}, p0, [x0, x0, lsl #3]
// CHECK-ENCODING: [0x00,0x80,0xe0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 e0 e0 <unknown>
-st1d za2v.d[w14, #1], p5, [x10, x21, lsl #3]
-// CHECK-INST: st1d {za2v.d[w14, #1]}, p5, [x10, x21, lsl #3]
+st1d za2v.d[w14, 1], p5, [x10, x21, lsl #3]
+// CHECK-INST: st1d {za2v.d[w14, 1]}, p5, [x10, x21, lsl #3]
// CHECK-ENCODING: [0x45,0xd5,0xf5,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 f5 e0 <unknown>
-st1d za3v.d[w15, #1], p3, [x13, x8, lsl #3]
-// CHECK-INST: st1d {za3v.d[w15, #1]}, p3, [x13, x8, lsl #3]
+st1d za3v.d[w15, 1], p3, [x13, x8, lsl #3]
+// CHECK-INST: st1d {za3v.d[w15, 1]}, p3, [x13, x8, lsl #3]
// CHECK-ENCODING: [0xa7,0xed,0xe8,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed e8 e0 <unknown>
-st1d za7v.d[w15, #1], p7, [sp]
-// CHECK-INST: st1d {za7v.d[w15, #1]}, p7, [sp]
+st1d za7v.d[w15, 1], p7, [sp]
+// CHECK-INST: st1d {za7v.d[w15, 1]}, p7, [sp]
// CHECK-ENCODING: [0xef,0xff,0xff,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff ff e0 <unknown>
-st1d za2v.d[w12, #1], p3, [x17, x16, lsl #3]
-// CHECK-INST: st1d {za2v.d[w12, #1]}, p3, [x17, x16, lsl #3]
+st1d za2v.d[w12, 1], p3, [x17, x16, lsl #3]
+// CHECK-INST: st1d {za2v.d[w12, 1]}, p3, [x17, x16, lsl #3]
// CHECK-ENCODING: [0x25,0x8e,0xf0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e f0 e0 <unknown>
-st1d za0v.d[w12, #1], p1, [x1, x30, lsl #3]
-// CHECK-INST: st1d {za0v.d[w12, #1]}, p1, [x1, x30, lsl #3]
+st1d za0v.d[w12, 1], p1, [x1, x30, lsl #3]
+// CHECK-INST: st1d {za0v.d[w12, 1]}, p1, [x1, x30, lsl #3]
// CHECK-ENCODING: [0x21,0x84,0xfe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 fe e0 <unknown>
-st1d za4v.d[w14, #0], p5, [x19, x20, lsl #3]
-// CHECK-INST: st1d {za4v.d[w14, #0]}, p5, [x19, x20, lsl #3]
+st1d za4v.d[w14, 0], p5, [x19, x20, lsl #3]
+// CHECK-INST: st1d {za4v.d[w14, 0]}, p5, [x19, x20, lsl #3]
// CHECK-ENCODING: [0x68,0xd6,0xf4,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 f4 e0 <unknown>
-st1d za0v.d[w12, #0], p6, [x12, x2, lsl #3]
-// CHECK-INST: st1d {za0v.d[w12, #0]}, p6, [x12, x2, lsl #3]
+st1d za0v.d[w12, 0], p6, [x12, x2, lsl #3]
+// CHECK-INST: st1d {za0v.d[w12, 0]}, p6, [x12, x2, lsl #3]
// CHECK-ENCODING: [0x80,0x99,0xe2,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 e2 e0 <unknown>
-st1d za0v.d[w14, #1], p2, [x1, x26, lsl #3]
-// CHECK-INST: st1d {za0v.d[w14, #1]}, p2, [x1, x26, lsl #3]
+st1d za0v.d[w14, 1], p2, [x1, x26, lsl #3]
+// CHECK-INST: st1d {za0v.d[w14, 1]}, p2, [x1, x26, lsl #3]
// CHECK-ENCODING: [0x21,0xc8,0xfa,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 fa e0 <unknown>
-st1d za6v.d[w12, #1], p2, [x22, x30, lsl #3]
-// CHECK-INST: st1d {za6v.d[w12, #1]}, p2, [x22, x30, lsl #3]
+st1d za6v.d[w12, 1], p2, [x22, x30, lsl #3]
+// CHECK-INST: st1d {za6v.d[w12, 1]}, p2, [x22, x30, lsl #3]
// CHECK-ENCODING: [0xcd,0x8a,0xfe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a fe e0 <unknown>
-st1d za1v.d[w15, #0], p5, [x9, x1, lsl #3]
-// CHECK-INST: st1d {za1v.d[w15, #0]}, p5, [x9, x1, lsl #3]
+st1d za1v.d[w15, 0], p5, [x9, x1, lsl #3]
+// CHECK-INST: st1d {za1v.d[w15, 0]}, p5, [x9, x1, lsl #3]
// CHECK-ENCODING: [0x22,0xf5,0xe1,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 e1 e0 <unknown>
-st1d za3v.d[w13, #1], p2, [x12, x11, lsl #3]
-// CHECK-INST: st1d {za3v.d[w13, #1]}, p2, [x12, x11, lsl #3]
+st1d za3v.d[w13, 1], p2, [x12, x11, lsl #3]
+// CHECK-INST: st1d {za3v.d[w13, 1]}, p2, [x12, x11, lsl #3]
// CHECK-ENCODING: [0x87,0xa9,0xeb,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 eb e0 <unknown>
diff --git a/llvm/test/MC/AArch64/SME/st1h-diagnostics.s b/llvm/test/MC/AArch64/SME/st1h-diagnostics.s
index 448ecb5e9b7f8..8493729570bce 100644
--- a/llvm/test/MC/AArch64/SME/st1h-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/st1h-diagnostics.s
@@ -3,32 +3,32 @@
// ------------------------------------------------------------------------- //
// Invalid tile (expected: za[0-1]h.h or za[0-1]v.h)
-st1h {za2h.h[w12, #0]}, p0, [x0]
+st1h {za2h.h[w12, 0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: st1h {za2h.h[w12, #0]}, p0, [x0]
+// CHECK-NEXT: st1h {za2h.h[w12, 0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1h {za[w12, #0]}, p0/z, [x0]
+st1h {za[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-1]h.h or za[0-1]v.h
-// CHECK-NEXT: st1h {za[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: st1h {za[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1h {za0.b[w12, #0]}, p0/z, [x0]
+st1h {za0.b[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-1]h.h or za[0-1]v.h
-// CHECK-NEXT: st1h {za0.b[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: st1h {za0.b[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid vector select register (expected: w12-w15)
-st1h {za0h.h[w11, #0]}, p0, [x0]
+st1h {za0h.h[w11, 0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: st1h {za0h.h[w11, #0]}, p0, [x0]
+// CHECK-NEXT: st1h {za0h.h[w11, 0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1h {za0h.h[w16, #0]}, p0, [x0]
+st1h {za0h.h[w16, 0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: st1h {za0h.h[w16, #0]}, p0, [x0]
+// CHECK-NEXT: st1h {za0h.h[w16, 0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
@@ -39,46 +39,46 @@ st1h {za0h.h[w12]}, p0, [x0]
// CHECK-NEXT: st1h {za0h.h[w12]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1h {za0h.h[w12, #8]}, p0, [x0]
+st1h {za0h.h[w12, 8]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
-// CHECK-NEXT: st1h {za0h.h[w12, #8]}, p0, [x0]
+// CHECK-NEXT: st1h {za0h.h[w12, 8]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate (expected: p0-p7)
-st1h {za0h.h[w12, #0]}, p8, [x0]
+st1h {za0h.h[w12, 0]}, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
-// CHECK-NEXT: st1h {za0h.h[w12, #0]}, p8, [x0]
+// CHECK-NEXT: st1h {za0h.h[w12, 0]}, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Unexpected predicate qualifier
-st1h {za0h.h[w12, #0]}, p0/z, [x0]
+st1h {za0h.h[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: st1h {za0h.h[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: st1h {za0h.h[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1h {za0h.h[w12, #0]}, p0/m, [x0]
+st1h {za0h.h[w12, 0]}, p0/m, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: st1h {za0h.h[w12, #0]}, p0/m, [x0]
+// CHECK-NEXT: st1h {za0h.h[w12, 0]}, p0/m, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid memory operands
-st1h {za0h.h[w12, #0]}, p0, [w0]
+st1h {za0h.h[w12, 0]}, p0, [w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: st1h {za0h.h[w12, #0]}, p0, [w0]
+// CHECK-NEXT: st1h {za0h.h[w12, 0]}, p0, [w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1h {za0h.h[w12, #0]}, p0, [x0, w0]
+st1h {za0h.h[w12, 0]}, p0, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
-// CHECK-NEXT: st1h {za0h.h[w12, #0]}, p0, [x0, w0]
+// CHECK-NEXT: st1h {za0h.h[w12, 0]}, p0, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1h {za0h.h[w12, #0]}, p0, [x0, x0, lsl #2]
+st1h {za0h.h[w12, 0]}, p0, [x0, x0, lsl #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
-// CHECK-NEXT: st1h {za0h.h[w12, #0]}, p0, [x0, x0, lsl #2]
+// CHECK-NEXT: st1h {za0h.h[w12, 0]}, p0, [x0, x0, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/st1h.s b/llvm/test/MC/AArch64/SME/st1h.s
index bd28e11d7cfac..1fcd3a9c125a0 100644
--- a/llvm/test/MC/AArch64/SME/st1h.s
+++ b/llvm/test/MC/AArch64/SME/st1h.s
@@ -15,146 +15,146 @@
// --------------------------------------------------------------------------//
// Horizontal
-st1h {za0h.h[w12, #0]}, p0, [x0, x0, lsl #1]
-// CHECK-INST: st1h {za0h.h[w12, #0]}, p0, [x0, x0, lsl #1]
+st1h {za0h.h[w12, 0]}, p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h {za0h.h[w12, 0]}, p0, [x0, x0, lsl #1]
// CHECK-ENCODING: [0x00,0x00,0x60,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 60 e0 <unknown>
-st1h {za0h.h[w14, #5]}, p5, [x10, x21, lsl #1]
-// CHECK-INST: st1h {za0h.h[w14, #5]}, p5, [x10, x21, lsl #1]
+st1h {za0h.h[w14, 5]}, p5, [x10, x21, lsl #1]
+// CHECK-INST: st1h {za0h.h[w14, 5]}, p5, [x10, x21, lsl #1]
// CHECK-ENCODING: [0x45,0x55,0x75,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 75 e0 <unknown>
-st1h {za0h.h[w15, #7]}, p3, [x13, x8, lsl #1]
-// CHECK-INST: st1h {za0h.h[w15, #7]}, p3, [x13, x8, lsl #1]
+st1h {za0h.h[w15, 7]}, p3, [x13, x8, lsl #1]
+// CHECK-INST: st1h {za0h.h[w15, 7]}, p3, [x13, x8, lsl #1]
// CHECK-ENCODING: [0xa7,0x6d,0x68,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 68 e0 <unknown>
-st1h {za1h.h[w15, #7]}, p7, [sp]
-// CHECK-INST: st1h {za1h.h[w15, #7]}, p7, [sp]
+st1h {za1h.h[w15, 7]}, p7, [sp]
+// CHECK-INST: st1h {za1h.h[w15, 7]}, p7, [sp]
// CHECK-ENCODING: [0xef,0x7f,0x7f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 7f e0 <unknown>
-st1h {za0h.h[w12, #5]}, p3, [x17, x16, lsl #1]
-// CHECK-INST: st1h {za0h.h[w12, #5]}, p3, [x17, x16, lsl #1]
+st1h {za0h.h[w12, 5]}, p3, [x17, x16, lsl #1]
+// CHECK-INST: st1h {za0h.h[w12, 5]}, p3, [x17, x16, lsl #1]
// CHECK-ENCODING: [0x25,0x0e,0x70,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 70 e0 <unknown>
-st1h {za0h.h[w12, #1]}, p1, [x1, x30, lsl #1]
-// CHECK-INST: st1h {za0h.h[w12, #1]}, p1, [x1, x30, lsl #1]
+st1h {za0h.h[w12, 1]}, p1, [x1, x30, lsl #1]
+// CHECK-INST: st1h {za0h.h[w12, 1]}, p1, [x1, x30, lsl #1]
// CHECK-ENCODING: [0x21,0x04,0x7e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 7e e0 <unknown>
-st1h {za1h.h[w14, #0]}, p5, [x19, x20, lsl #1]
-// CHECK-INST: st1h {za1h.h[w14, #0]}, p5, [x19, x20, lsl #1]
+st1h {za1h.h[w14, 0]}, p5, [x19, x20, lsl #1]
+// CHECK-INST: st1h {za1h.h[w14, 0]}, p5, [x19, x20, lsl #1]
// CHECK-ENCODING: [0x68,0x56,0x74,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 74 e0 <unknown>
-st1h {za0h.h[w12, #0]}, p6, [x12, x2, lsl #1]
-// CHECK-INST: st1h {za0h.h[w12, #0]}, p6, [x12, x2, lsl #1]
+st1h {za0h.h[w12, 0]}, p6, [x12, x2, lsl #1]
+// CHECK-INST: st1h {za0h.h[w12, 0]}, p6, [x12, x2, lsl #1]
// CHECK-ENCODING: [0x80,0x19,0x62,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 62 e0 <unknown>
-st1h {za0h.h[w14, #1]}, p2, [x1, x26, lsl #1]
-// CHECK-INST: st1h {za0h.h[w14, #1]}, p2, [x1, x26, lsl #1]
+st1h {za0h.h[w14, 1]}, p2, [x1, x26, lsl #1]
+// CHECK-INST: st1h {za0h.h[w14, 1]}, p2, [x1, x26, lsl #1]
// CHECK-ENCODING: [0x21,0x48,0x7a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 7a e0 <unknown>
-st1h {za1h.h[w12, #5]}, p2, [x22, x30, lsl #1]
-// CHECK-INST: st1h {za1h.h[w12, #5]}, p2, [x22, x30, lsl #1]
+st1h {za1h.h[w12, 5]}, p2, [x22, x30, lsl #1]
+// CHECK-INST: st1h {za1h.h[w12, 5]}, p2, [x22, x30, lsl #1]
// CHECK-ENCODING: [0xcd,0x0a,0x7e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 7e e0 <unknown>
-st1h {za0h.h[w15, #2]}, p5, [x9, x1, lsl #1]
-// CHECK-INST: st1h {za0h.h[w15, #2]}, p5, [x9, x1, lsl #1]
+st1h {za0h.h[w15, 2]}, p5, [x9, x1, lsl #1]
+// CHECK-INST: st1h {za0h.h[w15, 2]}, p5, [x9, x1, lsl #1]
// CHECK-ENCODING: [0x22,0x75,0x61,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 61 e0 <unknown>
-st1h {za0h.h[w13, #7]}, p2, [x12, x11, lsl #1]
-// CHECK-INST: st1h {za0h.h[w13, #7]}, p2, [x12, x11, lsl #1]
+st1h {za0h.h[w13, 7]}, p2, [x12, x11, lsl #1]
+// CHECK-INST: st1h {za0h.h[w13, 7]}, p2, [x12, x11, lsl #1]
// CHECK-ENCODING: [0x87,0x29,0x6b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 6b e0 <unknown>
-st1h za0h.h[w12, #0], p0, [x0, x0, lsl #1]
-// CHECK-INST: st1h {za0h.h[w12, #0]}, p0, [x0, x0, lsl #1]
+st1h za0h.h[w12, 0], p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h {za0h.h[w12, 0]}, p0, [x0, x0, lsl #1]
// CHECK-ENCODING: [0x00,0x00,0x60,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 60 e0 <unknown>
-st1h za0h.h[w14, #5], p5, [x10, x21, lsl #1]
-// CHECK-INST: st1h {za0h.h[w14, #5]}, p5, [x10, x21, lsl #1]
+st1h za0h.h[w14, 5], p5, [x10, x21, lsl #1]
+// CHECK-INST: st1h {za0h.h[w14, 5]}, p5, [x10, x21, lsl #1]
// CHECK-ENCODING: [0x45,0x55,0x75,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 75 e0 <unknown>
-st1h za0h.h[w15, #7], p3, [x13, x8, lsl #1]
-// CHECK-INST: st1h {za0h.h[w15, #7]}, p3, [x13, x8, lsl #1]
+st1h za0h.h[w15, 7], p3, [x13, x8, lsl #1]
+// CHECK-INST: st1h {za0h.h[w15, 7]}, p3, [x13, x8, lsl #1]
// CHECK-ENCODING: [0xa7,0x6d,0x68,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 68 e0 <unknown>
-st1h za1h.h[w15, #7], p7, [sp]
-// CHECK-INST: st1h {za1h.h[w15, #7]}, p7, [sp]
+st1h za1h.h[w15, 7], p7, [sp]
+// CHECK-INST: st1h {za1h.h[w15, 7]}, p7, [sp]
// CHECK-ENCODING: [0xef,0x7f,0x7f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f 7f e0 <unknown>
-st1h za0h.h[w12, #5], p3, [x17, x16, lsl #1]
-// CHECK-INST: st1h {za0h.h[w12, #5]}, p3, [x17, x16, lsl #1]
+st1h za0h.h[w12, 5], p3, [x17, x16, lsl #1]
+// CHECK-INST: st1h {za0h.h[w12, 5]}, p3, [x17, x16, lsl #1]
// CHECK-ENCODING: [0x25,0x0e,0x70,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e 70 e0 <unknown>
-st1h za0h.h[w12, #1], p1, [x1, x30, lsl #1]
-// CHECK-INST: st1h {za0h.h[w12, #1]}, p1, [x1, x30, lsl #1]
+st1h za0h.h[w12, 1], p1, [x1, x30, lsl #1]
+// CHECK-INST: st1h {za0h.h[w12, 1]}, p1, [x1, x30, lsl #1]
// CHECK-ENCODING: [0x21,0x04,0x7e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 7e e0 <unknown>
-st1h za1h.h[w14, #0], p5, [x19, x20, lsl #1]
-// CHECK-INST: st1h {za1h.h[w14, #0]}, p5, [x19, x20, lsl #1]
+st1h za1h.h[w14, 0], p5, [x19, x20, lsl #1]
+// CHECK-INST: st1h {za1h.h[w14, 0]}, p5, [x19, x20, lsl #1]
// CHECK-ENCODING: [0x68,0x56,0x74,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 74 e0 <unknown>
-st1h za0h.h[w12, #0], p6, [x12, x2, lsl #1]
-// CHECK-INST: st1h {za0h.h[w12, #0]}, p6, [x12, x2, lsl #1]
+st1h za0h.h[w12, 0], p6, [x12, x2, lsl #1]
+// CHECK-INST: st1h {za0h.h[w12, 0]}, p6, [x12, x2, lsl #1]
// CHECK-ENCODING: [0x80,0x19,0x62,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 62 e0 <unknown>
-st1h za0h.h[w14, #1], p2, [x1, x26, lsl #1]
-// CHECK-INST: st1h {za0h.h[w14, #1]}, p2, [x1, x26, lsl #1]
+st1h za0h.h[w14, 1], p2, [x1, x26, lsl #1]
+// CHECK-INST: st1h {za0h.h[w14, 1]}, p2, [x1, x26, lsl #1]
// CHECK-ENCODING: [0x21,0x48,0x7a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 7a e0 <unknown>
-st1h za1h.h[w12, #5], p2, [x22, x30, lsl #1]
-// CHECK-INST: st1h {za1h.h[w12, #5]}, p2, [x22, x30, lsl #1]
+st1h za1h.h[w12, 5], p2, [x22, x30, lsl #1]
+// CHECK-INST: st1h {za1h.h[w12, 5]}, p2, [x22, x30, lsl #1]
// CHECK-ENCODING: [0xcd,0x0a,0x7e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a 7e e0 <unknown>
-st1h za0h.h[w15, #2], p5, [x9, x1, lsl #1]
-// CHECK-INST: st1h {za0h.h[w15, #2]}, p5, [x9, x1, lsl #1]
+st1h za0h.h[w15, 2], p5, [x9, x1, lsl #1]
+// CHECK-INST: st1h {za0h.h[w15, 2]}, p5, [x9, x1, lsl #1]
// CHECK-ENCODING: [0x22,0x75,0x61,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 61 e0 <unknown>
-st1h za0h.h[w13, #7], p2, [x12, x11, lsl #1]
-// CHECK-INST: st1h {za0h.h[w13, #7]}, p2, [x12, x11, lsl #1]
+st1h za0h.h[w13, 7], p2, [x12, x11, lsl #1]
+// CHECK-INST: st1h {za0h.h[w13, 7]}, p2, [x12, x11, lsl #1]
// CHECK-ENCODING: [0x87,0x29,0x6b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 6b e0 <unknown>
@@ -162,146 +162,146 @@ st1h za0h.h[w13, #7], p2, [x12, x11, lsl #1]
// --------------------------------------------------------------------------//
// Vertical
-st1h {za0v.h[w12, #0]}, p0, [x0, x0, lsl #1]
-// CHECK-INST: st1h {za0v.h[w12, #0]}, p0, [x0, x0, lsl #1]
+st1h {za0v.h[w12, 0]}, p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h {za0v.h[w12, 0]}, p0, [x0, x0, lsl #1]
// CHECK-ENCODING: [0x00,0x80,0x60,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 60 e0 <unknown>
-st1h {za0v.h[w14, #5]}, p5, [x10, x21, lsl #1]
-// CHECK-INST: st1h {za0v.h[w14, #5]}, p5, [x10, x21, lsl #1]
+st1h {za0v.h[w14, 5]}, p5, [x10, x21, lsl #1]
+// CHECK-INST: st1h {za0v.h[w14, 5]}, p5, [x10, x21, lsl #1]
// CHECK-ENCODING: [0x45,0xd5,0x75,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 75 e0 <unknown>
-st1h {za0v.h[w15, #7]}, p3, [x13, x8, lsl #1]
-// CHECK-INST: st1h {za0v.h[w15, #7]}, p3, [x13, x8, lsl #1]
+st1h {za0v.h[w15, 7]}, p3, [x13, x8, lsl #1]
+// CHECK-INST: st1h {za0v.h[w15, 7]}, p3, [x13, x8, lsl #1]
// CHECK-ENCODING: [0xa7,0xed,0x68,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 68 e0 <unknown>
-st1h {za1v.h[w15, #7]}, p7, [sp]
-// CHECK-INST: st1h {za1v.h[w15, #7]}, p7, [sp]
+st1h {za1v.h[w15, 7]}, p7, [sp]
+// CHECK-INST: st1h {za1v.h[w15, 7]}, p7, [sp]
// CHECK-ENCODING: [0xef,0xff,0x7f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 7f e0 <unknown>
-st1h {za0v.h[w12, #5]}, p3, [x17, x16, lsl #1]
-// CHECK-INST: st1h {za0v.h[w12, #5]}, p3, [x17, x16, lsl #1]
+st1h {za0v.h[w12, 5]}, p3, [x17, x16, lsl #1]
+// CHECK-INST: st1h {za0v.h[w12, 5]}, p3, [x17, x16, lsl #1]
// CHECK-ENCODING: [0x25,0x8e,0x70,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 70 e0 <unknown>
-st1h {za0v.h[w12, #1]}, p1, [x1, x30, lsl #1]
-// CHECK-INST: st1h {za0v.h[w12, #1]}, p1, [x1, x30, lsl #1]
+st1h {za0v.h[w12, 1]}, p1, [x1, x30, lsl #1]
+// CHECK-INST: st1h {za0v.h[w12, 1]}, p1, [x1, x30, lsl #1]
// CHECK-ENCODING: [0x21,0x84,0x7e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 7e e0 <unknown>
-st1h {za1v.h[w14, #0]}, p5, [x19, x20, lsl #1]
-// CHECK-INST: st1h {za1v.h[w14, #0]}, p5, [x19, x20, lsl #1]
+st1h {za1v.h[w14, 0]}, p5, [x19, x20, lsl #1]
+// CHECK-INST: st1h {za1v.h[w14, 0]}, p5, [x19, x20, lsl #1]
// CHECK-ENCODING: [0x68,0xd6,0x74,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 74 e0 <unknown>
-st1h {za0v.h[w12, #0]}, p6, [x12, x2, lsl #1]
-// CHECK-INST: st1h {za0v.h[w12, #0]}, p6, [x12, x2, lsl #1]
+st1h {za0v.h[w12, 0]}, p6, [x12, x2, lsl #1]
+// CHECK-INST: st1h {za0v.h[w12, 0]}, p6, [x12, x2, lsl #1]
// CHECK-ENCODING: [0x80,0x99,0x62,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 62 e0 <unknown>
-st1h {za0v.h[w14, #1]}, p2, [x1, x26, lsl #1]
-// CHECK-INST: st1h {za0v.h[w14, #1]}, p2, [x1, x26, lsl #1]
+st1h {za0v.h[w14, 1]}, p2, [x1, x26, lsl #1]
+// CHECK-INST: st1h {za0v.h[w14, 1]}, p2, [x1, x26, lsl #1]
// CHECK-ENCODING: [0x21,0xc8,0x7a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 7a e0 <unknown>
-st1h {za1v.h[w12, #5]}, p2, [x22, x30, lsl #1]
-// CHECK-INST: st1h {za1v.h[w12, #5]}, p2, [x22, x30, lsl #1]
+st1h {za1v.h[w12, 5]}, p2, [x22, x30, lsl #1]
+// CHECK-INST: st1h {za1v.h[w12, 5]}, p2, [x22, x30, lsl #1]
// CHECK-ENCODING: [0xcd,0x8a,0x7e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 7e e0 <unknown>
-st1h {za0v.h[w15, #2]}, p5, [x9, x1, lsl #1]
-// CHECK-INST: st1h {za0v.h[w15, #2]}, p5, [x9, x1, lsl #1]
+st1h {za0v.h[w15, 2]}, p5, [x9, x1, lsl #1]
+// CHECK-INST: st1h {za0v.h[w15, 2]}, p5, [x9, x1, lsl #1]
// CHECK-ENCODING: [0x22,0xf5,0x61,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 61 e0 <unknown>
-st1h {za0v.h[w13, #7]}, p2, [x12, x11, lsl #1]
-// CHECK-INST: st1h {za0v.h[w13, #7]}, p2, [x12, x11, lsl #1]
+st1h {za0v.h[w13, 7]}, p2, [x12, x11, lsl #1]
+// CHECK-INST: st1h {za0v.h[w13, 7]}, p2, [x12, x11, lsl #1]
// CHECK-ENCODING: [0x87,0xa9,0x6b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 6b e0 <unknown>
-st1h za0v.h[w12, #0], p0, [x0, x0, lsl #1]
-// CHECK-INST: st1h {za0v.h[w12, #0]}, p0, [x0, x0, lsl #1]
+st1h za0v.h[w12, 0], p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h {za0v.h[w12, 0]}, p0, [x0, x0, lsl #1]
// CHECK-ENCODING: [0x00,0x80,0x60,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 60 e0 <unknown>
-st1h za0v.h[w14, #5], p5, [x10, x21, lsl #1]
-// CHECK-INST: st1h {za0v.h[w14, #5]}, p5, [x10, x21, lsl #1]
+st1h za0v.h[w14, 5], p5, [x10, x21, lsl #1]
+// CHECK-INST: st1h {za0v.h[w14, 5]}, p5, [x10, x21, lsl #1]
// CHECK-ENCODING: [0x45,0xd5,0x75,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 75 e0 <unknown>
-st1h za0v.h[w15, #7], p3, [x13, x8, lsl #1]
-// CHECK-INST: st1h {za0v.h[w15, #7]}, p3, [x13, x8, lsl #1]
+st1h za0v.h[w15, 7], p3, [x13, x8, lsl #1]
+// CHECK-INST: st1h {za0v.h[w15, 7]}, p3, [x13, x8, lsl #1]
// CHECK-ENCODING: [0xa7,0xed,0x68,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed 68 e0 <unknown>
-st1h za1v.h[w15, #7], p7, [sp]
-// CHECK-INST: st1h {za1v.h[w15, #7]}, p7, [sp]
+st1h za1v.h[w15, 7], p7, [sp]
+// CHECK-INST: st1h {za1v.h[w15, 7]}, p7, [sp]
// CHECK-ENCODING: [0xef,0xff,0x7f,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff 7f e0 <unknown>
-st1h za0v.h[w12, #5], p3, [x17, x16, lsl #1]
-// CHECK-INST: st1h {za0v.h[w12, #5]}, p3, [x17, x16, lsl #1]
+st1h za0v.h[w12, 5], p3, [x17, x16, lsl #1]
+// CHECK-INST: st1h {za0v.h[w12, 5]}, p3, [x17, x16, lsl #1]
// CHECK-ENCODING: [0x25,0x8e,0x70,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e 70 e0 <unknown>
-st1h za0v.h[w12, #1], p1, [x1, x30, lsl #1]
-// CHECK-INST: st1h {za0v.h[w12, #1]}, p1, [x1, x30, lsl #1]
+st1h za0v.h[w12, 1], p1, [x1, x30, lsl #1]
+// CHECK-INST: st1h {za0v.h[w12, 1]}, p1, [x1, x30, lsl #1]
// CHECK-ENCODING: [0x21,0x84,0x7e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 7e e0 <unknown>
-st1h za1v.h[w14, #0], p5, [x19, x20, lsl #1]
-// CHECK-INST: st1h {za1v.h[w14, #0]}, p5, [x19, x20, lsl #1]
+st1h za1v.h[w14, 0], p5, [x19, x20, lsl #1]
+// CHECK-INST: st1h {za1v.h[w14, 0]}, p5, [x19, x20, lsl #1]
// CHECK-ENCODING: [0x68,0xd6,0x74,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 74 e0 <unknown>
-st1h za0v.h[w12, #0], p6, [x12, x2, lsl #1]
-// CHECK-INST: st1h {za0v.h[w12, #0]}, p6, [x12, x2, lsl #1]
+st1h za0v.h[w12, 0], p6, [x12, x2, lsl #1]
+// CHECK-INST: st1h {za0v.h[w12, 0]}, p6, [x12, x2, lsl #1]
// CHECK-ENCODING: [0x80,0x99,0x62,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 62 e0 <unknown>
-st1h za0v.h[w14, #1], p2, [x1, x26, lsl #1]
-// CHECK-INST: st1h {za0v.h[w14, #1]}, p2, [x1, x26, lsl #1]
+st1h za0v.h[w14, 1], p2, [x1, x26, lsl #1]
+// CHECK-INST: st1h {za0v.h[w14, 1]}, p2, [x1, x26, lsl #1]
// CHECK-ENCODING: [0x21,0xc8,0x7a,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 7a e0 <unknown>
-st1h za1v.h[w12, #5], p2, [x22, x30, lsl #1]
-// CHECK-INST: st1h {za1v.h[w12, #5]}, p2, [x22, x30, lsl #1]
+st1h za1v.h[w12, 5], p2, [x22, x30, lsl #1]
+// CHECK-INST: st1h {za1v.h[w12, 5]}, p2, [x22, x30, lsl #1]
// CHECK-ENCODING: [0xcd,0x8a,0x7e,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a 7e e0 <unknown>
-st1h za0v.h[w15, #2], p5, [x9, x1, lsl #1]
-// CHECK-INST: st1h {za0v.h[w15, #2]}, p5, [x9, x1, lsl #1]
+st1h za0v.h[w15, 2], p5, [x9, x1, lsl #1]
+// CHECK-INST: st1h {za0v.h[w15, 2]}, p5, [x9, x1, lsl #1]
// CHECK-ENCODING: [0x22,0xf5,0x61,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 61 e0 <unknown>
-st1h za0v.h[w13, #7], p2, [x12, x11, lsl #1]
-// CHECK-INST: st1h {za0v.h[w13, #7]}, p2, [x12, x11, lsl #1]
+st1h za0v.h[w13, 7], p2, [x12, x11, lsl #1]
+// CHECK-INST: st1h {za0v.h[w13, 7]}, p2, [x12, x11, lsl #1]
// CHECK-ENCODING: [0x87,0xa9,0x6b,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 6b e0 <unknown>
diff --git a/llvm/test/MC/AArch64/SME/st1q-diagnostics.s b/llvm/test/MC/AArch64/SME/st1q-diagnostics.s
index 1af0d2c4292aa..dae09a9bcc557 100644
--- a/llvm/test/MC/AArch64/SME/st1q-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/st1q-diagnostics.s
@@ -3,69 +3,82 @@
// ------------------------------------------------------------------------- //
// Invalid tile (expected: za[0-15]h.q or za[0-15]v.q)
-st1q {za16h.q[w12]}, p0, [x0]
+st1q {za16h.q[w12, 0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: st1q {za16h.q[w12]}, p0, [x0]
+// CHECK-NEXT: st1q {za16h.q[w12, 0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1q {za[w12]}, p0/z, [x0]
+st1q {za[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-15]h.q or za[0-15]v.q
-// CHECK-NEXT: st1q {za[w12]}, p0/z, [x0]
+// CHECK-NEXT: st1q {za[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1q {za7v.d[w12]}, p0/z, [x0]
+st1q {za7v.d[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-15]h.q or za[0-15]v.q
-// CHECK-NEXT: st1q {za7v.d[w12]}, p0/z, [x0]
+// CHECK-NEXT: st1q {za7v.d[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid vector select register (expected: w12-w15)
-st1q {za0h.q[w11]}, p0, [x0]
+st1q {za0h.q[w11, 0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: st1q {za0h.q[w11]}, p0, [x0]
+// CHECK-NEXT: st1q {za0h.q[w11, 0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1q {za0h.q[w16]}, p0, [x0]
+st1q {za0h.q[w16, 0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: st1q {za0h.q[w16]}, p0, [x0]
+// CHECK-NEXT: st1q {za0h.q[w16, 0]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select offset (expected: 0)
+
+st1q {za0h.q[w12]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be 0.
+// CHECK-NEXT: st1q {za0h.q[w12]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1q {za0h.q[w12, 1]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be 0.
+// CHECK-NEXT: st1q {za0h.q[w12, 1]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate (expected: p0-p7)
-st1q {za0h.q[w12]}, p8, [x0]
+st1q {za0h.q[w12, 0]}, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
-// CHECK-NEXT: st1q {za0h.q[w12]}, p8, [x0]
+// CHECK-NEXT: st1q {za0h.q[w12, 0]}, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Unexpected predicate qualifier
-st1q {za0h.q[w12]}, p0/z, [x0]
+st1q {za0h.q[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: st1q {za0h.q[w12]}, p0/z, [x0]
+// CHECK-NEXT: st1q {za0h.q[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1q {za0h.q[w12]}, p0/m, [x0]
+st1q {za0h.q[w12, 0]}, p0/m, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: st1q {za0h.q[w12]}, p0/m, [x0]
+// CHECK-NEXT: st1q {za0h.q[w12, 0]}, p0/m, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid memory operands
-st1q {za0h.q[w12]}, p0, [w0]
+st1q {za0h.q[w12, 0]}, p0, [w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: st1q {za0h.q[w12]}, p0, [w0]
+// CHECK-NEXT: st1q {za0h.q[w12, 0]}, p0, [w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1q {za0h.q[w12]}, p0, [x0, w0]
+st1q {za0h.q[w12, 0]}, p0, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #4'
-// CHECK-NEXT: st1q {za0h.q[w12]}, p0, [x0, w0]
+// CHECK-NEXT: st1q {za0h.q[w12, 0]}, p0, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1q {za0h.q[w12]}, p0, [x0, x0, lsl #5]
+st1q {za0h.q[w12, 0]}, p0, [x0, x0, lsl #5]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #4'
-// CHECK-NEXT: st1q {za0h.q[w12]}, p0, [x0, x0, lsl #5]
+// CHECK-NEXT: st1q {za0h.q[w12, 0]}, p0, [x0, x0, lsl #5]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/st1q.s b/llvm/test/MC/AArch64/SME/st1q.s
index 4b453185334f5..20c2e400741d8 100644
--- a/llvm/test/MC/AArch64/SME/st1q.s
+++ b/llvm/test/MC/AArch64/SME/st1q.s
@@ -15,146 +15,146 @@
// --------------------------------------------------------------------------//
// Horizontal
-st1q {za0h.q[w12]}, p0, [x0, x0, lsl #4]
-// CHECK-INST: st1q {za0h.q[w12]}, p0, [x0, x0, lsl #4]
+st1q {za0h.q[w12, 0]}, p0, [x0, x0, lsl #4]
+// CHECK-INST: st1q {za0h.q[w12, 0]}, p0, [x0, x0, lsl #4]
// CHECK-ENCODING: [0x00,0x00,0xe0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 e0 e1 <unknown>
-st1q {za5h.q[w14]}, p5, [x10, x21, lsl #4]
-// CHECK-INST: st1q {za5h.q[w14]}, p5, [x10, x21, lsl #4]
+st1q {za5h.q[w14, 0]}, p5, [x10, x21, lsl #4]
+// CHECK-INST: st1q {za5h.q[w14, 0]}, p5, [x10, x21, lsl #4]
// CHECK-ENCODING: [0x45,0x55,0xf5,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 f5 e1 <unknown>
-st1q {za7h.q[w15]}, p3, [x13, x8, lsl #4]
-// CHECK-INST: st1q {za7h.q[w15]}, p3, [x13, x8, lsl #4]
+st1q {za7h.q[w15, 0]}, p3, [x13, x8, lsl #4]
+// CHECK-INST: st1q {za7h.q[w15, 0]}, p3, [x13, x8, lsl #4]
// CHECK-ENCODING: [0xa7,0x6d,0xe8,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d e8 e1 <unknown>
-st1q {za15h.q[w15]}, p7, [sp]
-// CHECK-INST: st1q {za15h.q[w15]}, p7, [sp]
+st1q {za15h.q[w15, 0]}, p7, [sp]
+// CHECK-INST: st1q {za15h.q[w15, 0]}, p7, [sp]
// CHECK-ENCODING: [0xef,0x7f,0xff,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f ff e1 <unknown>
-st1q {za5h.q[w12]}, p3, [x17, x16, lsl #4]
-// CHECK-INST: st1q {za5h.q[w12]}, p3, [x17, x16, lsl #4]
+st1q {za5h.q[w12, 0]}, p3, [x17, x16, lsl #4]
+// CHECK-INST: st1q {za5h.q[w12, 0]}, p3, [x17, x16, lsl #4]
// CHECK-ENCODING: [0x25,0x0e,0xf0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e f0 e1 <unknown>
-st1q {za1h.q[w12]}, p1, [x1, x30, lsl #4]
-// CHECK-INST: st1q {za1h.q[w12]}, p1, [x1, x30, lsl #4]
+st1q {za1h.q[w12, 0]}, p1, [x1, x30, lsl #4]
+// CHECK-INST: st1q {za1h.q[w12, 0]}, p1, [x1, x30, lsl #4]
// CHECK-ENCODING: [0x21,0x04,0xfe,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 fe e1 <unknown>
-st1q {za8h.q[w14]}, p5, [x19, x20, lsl #4]
-// CHECK-INST: st1q {za8h.q[w14]}, p5, [x19, x20, lsl #4]
+st1q {za8h.q[w14, 0]}, p5, [x19, x20, lsl #4]
+// CHECK-INST: st1q {za8h.q[w14, 0]}, p5, [x19, x20, lsl #4]
// CHECK-ENCODING: [0x68,0x56,0xf4,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 f4 e1 <unknown>
-st1q {za0h.q[w12]}, p6, [x12, x2, lsl #4]
-// CHECK-INST: st1q {za0h.q[w12]}, p6, [x12, x2, lsl #4]
+st1q {za0h.q[w12, 0]}, p6, [x12, x2, lsl #4]
+// CHECK-INST: st1q {za0h.q[w12, 0]}, p6, [x12, x2, lsl #4]
// CHECK-ENCODING: [0x80,0x19,0xe2,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 e2 e1 <unknown>
-st1q {za1h.q[w14]}, p2, [x1, x26, lsl #4]
-// CHECK-INST: st1q {za1h.q[w14]}, p2, [x1, x26, lsl #4]
+st1q {za1h.q[w14, 0]}, p2, [x1, x26, lsl #4]
+// CHECK-INST: st1q {za1h.q[w14, 0]}, p2, [x1, x26, lsl #4]
// CHECK-ENCODING: [0x21,0x48,0xfa,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 fa e1 <unknown>
-st1q {za13h.q[w12]}, p2, [x22, x30, lsl #4]
-// CHECK-INST: st1q {za13h.q[w12]}, p2, [x22, x30, lsl #4]
+st1q {za13h.q[w12, 0]}, p2, [x22, x30, lsl #4]
+// CHECK-INST: st1q {za13h.q[w12, 0]}, p2, [x22, x30, lsl #4]
// CHECK-ENCODING: [0xcd,0x0a,0xfe,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a fe e1 <unknown>
-st1q {za2h.q[w15]}, p5, [x9, x1, lsl #4]
-// CHECK-INST: st1q {za2h.q[w15]}, p5, [x9, x1, lsl #4]
+st1q {za2h.q[w15, 0]}, p5, [x9, x1, lsl #4]
+// CHECK-INST: st1q {za2h.q[w15, 0]}, p5, [x9, x1, lsl #4]
// CHECK-ENCODING: [0x22,0x75,0xe1,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 e1 e1 <unknown>
-st1q {za7h.q[w13]}, p2, [x12, x11, lsl #4]
-// CHECK-INST: st1q {za7h.q[w13]}, p2, [x12, x11, lsl #4]
+st1q {za7h.q[w13, 0]}, p2, [x12, x11, lsl #4]
+// CHECK-INST: st1q {za7h.q[w13, 0]}, p2, [x12, x11, lsl #4]
// CHECK-ENCODING: [0x87,0x29,0xeb,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 eb e1 <unknown>
-st1q za0h.q[w12], p0, [x0, x0, lsl #4]
-// CHECK-INST: st1q {za0h.q[w12]}, p0, [x0, x0, lsl #4]
+st1q za0h.q[w12, 0], p0, [x0, x0, lsl #4]
+// CHECK-INST: st1q {za0h.q[w12, 0]}, p0, [x0, x0, lsl #4]
// CHECK-ENCODING: [0x00,0x00,0xe0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 e0 e1 <unknown>
-st1q za5h.q[w14], p5, [x10, x21, lsl #4]
-// CHECK-INST: st1q {za5h.q[w14]}, p5, [x10, x21, lsl #4]
+st1q za5h.q[w14, 0], p5, [x10, x21, lsl #4]
+// CHECK-INST: st1q {za5h.q[w14, 0]}, p5, [x10, x21, lsl #4]
// CHECK-ENCODING: [0x45,0x55,0xf5,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 f5 e1 <unknown>
-st1q za7h.q[w15], p3, [x13, x8, lsl #4]
-// CHECK-INST: st1q {za7h.q[w15]}, p3, [x13, x8, lsl #4]
+st1q za7h.q[w15, 0], p3, [x13, x8, lsl #4]
+// CHECK-INST: st1q {za7h.q[w15, 0]}, p3, [x13, x8, lsl #4]
// CHECK-ENCODING: [0xa7,0x6d,0xe8,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d e8 e1 <unknown>
-st1q za15h.q[w15], p7, [sp]
-// CHECK-INST: st1q {za15h.q[w15]}, p7, [sp]
+st1q za15h.q[w15, 0], p7, [sp]
+// CHECK-INST: st1q {za15h.q[w15, 0]}, p7, [sp]
// CHECK-ENCODING: [0xef,0x7f,0xff,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f ff e1 <unknown>
-st1q za5h.q[w12], p3, [x17, x16, lsl #4]
-// CHECK-INST: st1q {za5h.q[w12]}, p3, [x17, x16, lsl #4]
+st1q za5h.q[w12, 0], p3, [x17, x16, lsl #4]
+// CHECK-INST: st1q {za5h.q[w12, 0]}, p3, [x17, x16, lsl #4]
// CHECK-ENCODING: [0x25,0x0e,0xf0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e f0 e1 <unknown>
-st1q za1h.q[w12], p1, [x1, x30, lsl #4]
-// CHECK-INST: st1q {za1h.q[w12]}, p1, [x1, x30, lsl #4]
+st1q za1h.q[w12, 0], p1, [x1, x30, lsl #4]
+// CHECK-INST: st1q {za1h.q[w12, 0]}, p1, [x1, x30, lsl #4]
// CHECK-ENCODING: [0x21,0x04,0xfe,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 fe e1 <unknown>
-st1q za8h.q[w14], p5, [x19, x20, lsl #4]
-// CHECK-INST: st1q {za8h.q[w14]}, p5, [x19, x20, lsl #4]
+st1q za8h.q[w14, 0], p5, [x19, x20, lsl #4]
+// CHECK-INST: st1q {za8h.q[w14, 0]}, p5, [x19, x20, lsl #4]
// CHECK-ENCODING: [0x68,0x56,0xf4,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 f4 e1 <unknown>
-st1q za0h.q[w12], p6, [x12, x2, lsl #4]
-// CHECK-INST: st1q {za0h.q[w12]}, p6, [x12, x2, lsl #4]
+st1q za0h.q[w12, 0], p6, [x12, x2, lsl #4]
+// CHECK-INST: st1q {za0h.q[w12, 0]}, p6, [x12, x2, lsl #4]
// CHECK-ENCODING: [0x80,0x19,0xe2,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 e2 e1 <unknown>
-st1q za1h.q[w14], p2, [x1, x26, lsl #4]
-// CHECK-INST: st1q {za1h.q[w14]}, p2, [x1, x26, lsl #4]
+st1q za1h.q[w14, 0], p2, [x1, x26, lsl #4]
+// CHECK-INST: st1q {za1h.q[w14, 0]}, p2, [x1, x26, lsl #4]
// CHECK-ENCODING: [0x21,0x48,0xfa,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 fa e1 <unknown>
-st1q za13h.q[w12], p2, [x22, x30, lsl #4]
-// CHECK-INST: st1q {za13h.q[w12]}, p2, [x22, x30, lsl #4]
+st1q za13h.q[w12, 0], p2, [x22, x30, lsl #4]
+// CHECK-INST: st1q {za13h.q[w12, 0]}, p2, [x22, x30, lsl #4]
// CHECK-ENCODING: [0xcd,0x0a,0xfe,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a fe e1 <unknown>
-st1q za2h.q[w15], p5, [x9, x1, lsl #4]
-// CHECK-INST: st1q {za2h.q[w15]}, p5, [x9, x1, lsl #4]
+st1q za2h.q[w15, 0], p5, [x9, x1, lsl #4]
+// CHECK-INST: st1q {za2h.q[w15, 0]}, p5, [x9, x1, lsl #4]
// CHECK-ENCODING: [0x22,0x75,0xe1,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 e1 e1 <unknown>
-st1q za7h.q[w13], p2, [x12, x11, lsl #4]
-// CHECK-INST: st1q {za7h.q[w13]}, p2, [x12, x11, lsl #4]
+st1q za7h.q[w13, 0], p2, [x12, x11, lsl #4]
+// CHECK-INST: st1q {za7h.q[w13, 0]}, p2, [x12, x11, lsl #4]
// CHECK-ENCODING: [0x87,0x29,0xeb,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 eb e1 <unknown>
@@ -162,146 +162,146 @@ st1q za7h.q[w13], p2, [x12, x11, lsl #4]
// --------------------------------------------------------------------------//
// Vertical
-st1q {za0v.q[w12]}, p0, [x0, x0, lsl #4]
-// CHECK-INST: st1q {za0v.q[w12]}, p0, [x0, x0, lsl #4]
+st1q {za0v.q[w12, 0]}, p0, [x0, x0, lsl #4]
+// CHECK-INST: st1q {za0v.q[w12, 0]}, p0, [x0, x0, lsl #4]
// CHECK-ENCODING: [0x00,0x80,0xe0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 e0 e1 <unknown>
-st1q {za5v.q[w14]}, p5, [x10, x21, lsl #4]
-// CHECK-INST: st1q {za5v.q[w14]}, p5, [x10, x21, lsl #4]
+st1q {za5v.q[w14, 0]}, p5, [x10, x21, lsl #4]
+// CHECK-INST: st1q {za5v.q[w14, 0]}, p5, [x10, x21, lsl #4]
// CHECK-ENCODING: [0x45,0xd5,0xf5,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 f5 e1 <unknown>
-st1q {za7v.q[w15]}, p3, [x13, x8, lsl #4]
-// CHECK-INST: st1q {za7v.q[w15]}, p3, [x13, x8, lsl #4]
+st1q {za7v.q[w15, 0]}, p3, [x13, x8, lsl #4]
+// CHECK-INST: st1q {za7v.q[w15, 0]}, p3, [x13, x8, lsl #4]
// CHECK-ENCODING: [0xa7,0xed,0xe8,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed e8 e1 <unknown>
-st1q {za15v.q[w15]}, p7, [sp]
-// CHECK-INST: st1q {za15v.q[w15]}, p7, [sp]
+st1q {za15v.q[w15, 0]}, p7, [sp]
+// CHECK-INST: st1q {za15v.q[w15, 0]}, p7, [sp]
// CHECK-ENCODING: [0xef,0xff,0xff,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff ff e1 <unknown>
-st1q {za5v.q[w12]}, p3, [x17, x16, lsl #4]
-// CHECK-INST: st1q {za5v.q[w12]}, p3, [x17, x16, lsl #4]
+st1q {za5v.q[w12, 0]}, p3, [x17, x16, lsl #4]
+// CHECK-INST: st1q {za5v.q[w12, 0]}, p3, [x17, x16, lsl #4]
// CHECK-ENCODING: [0x25,0x8e,0xf0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e f0 e1 <unknown>
-st1q {za1v.q[w12]}, p1, [x1, x30, lsl #4]
-// CHECK-INST: st1q {za1v.q[w12]}, p1, [x1, x30, lsl #4]
+st1q {za1v.q[w12, 0]}, p1, [x1, x30, lsl #4]
+// CHECK-INST: st1q {za1v.q[w12, 0]}, p1, [x1, x30, lsl #4]
// CHECK-ENCODING: [0x21,0x84,0xfe,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 fe e1 <unknown>
-st1q {za8v.q[w14]}, p5, [x19, x20, lsl #4]
-// CHECK-INST: st1q {za8v.q[w14]}, p5, [x19, x20, lsl #4]
+st1q {za8v.q[w14, 0]}, p5, [x19, x20, lsl #4]
+// CHECK-INST: st1q {za8v.q[w14, 0]}, p5, [x19, x20, lsl #4]
// CHECK-ENCODING: [0x68,0xd6,0xf4,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 f4 e1 <unknown>
-st1q {za0v.q[w12]}, p6, [x12, x2, lsl #4]
-// CHECK-INST: st1q {za0v.q[w12]}, p6, [x12, x2, lsl #4]
+st1q {za0v.q[w12, 0]}, p6, [x12, x2, lsl #4]
+// CHECK-INST: st1q {za0v.q[w12, 0]}, p6, [x12, x2, lsl #4]
// CHECK-ENCODING: [0x80,0x99,0xe2,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 e2 e1 <unknown>
-st1q {za1v.q[w14]}, p2, [x1, x26, lsl #4]
-// CHECK-INST: st1q {za1v.q[w14]}, p2, [x1, x26, lsl #4]
+st1q {za1v.q[w14, 0]}, p2, [x1, x26, lsl #4]
+// CHECK-INST: st1q {za1v.q[w14, 0]}, p2, [x1, x26, lsl #4]
// CHECK-ENCODING: [0x21,0xc8,0xfa,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 fa e1 <unknown>
-st1q {za13v.q[w12]}, p2, [x22, x30, lsl #4]
-// CHECK-INST: st1q {za13v.q[w12]}, p2, [x22, x30, lsl #4]
+st1q {za13v.q[w12, 0]}, p2, [x22, x30, lsl #4]
+// CHECK-INST: st1q {za13v.q[w12, 0]}, p2, [x22, x30, lsl #4]
// CHECK-ENCODING: [0xcd,0x8a,0xfe,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a fe e1 <unknown>
-st1q {za2v.q[w15]}, p5, [x9, x1, lsl #4]
-// CHECK-INST: st1q {za2v.q[w15]}, p5, [x9, x1, lsl #4]
+st1q {za2v.q[w15, 0]}, p5, [x9, x1, lsl #4]
+// CHECK-INST: st1q {za2v.q[w15, 0]}, p5, [x9, x1, lsl #4]
// CHECK-ENCODING: [0x22,0xf5,0xe1,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 e1 e1 <unknown>
-st1q {za7v.q[w13]}, p2, [x12, x11, lsl #4]
-// CHECK-INST: st1q {za7v.q[w13]}, p2, [x12, x11, lsl #4]
+st1q {za7v.q[w13, 0]}, p2, [x12, x11, lsl #4]
+// CHECK-INST: st1q {za7v.q[w13, 0]}, p2, [x12, x11, lsl #4]
// CHECK-ENCODING: [0x87,0xa9,0xeb,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 eb e1 <unknown>
-st1q za0v.q[w12], p0, [x0, x0, lsl #4]
-// CHECK-INST: st1q {za0v.q[w12]}, p0, [x0, x0, lsl #4]
+st1q za0v.q[w12, 0], p0, [x0, x0, lsl #4]
+// CHECK-INST: st1q {za0v.q[w12, 0]}, p0, [x0, x0, lsl #4]
// CHECK-ENCODING: [0x00,0x80,0xe0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 e0 e1 <unknown>
-st1q za5v.q[w14], p5, [x10, x21, lsl #4]
-// CHECK-INST: st1q {za5v.q[w14]}, p5, [x10, x21, lsl #4]
+st1q za5v.q[w14, 0], p5, [x10, x21, lsl #4]
+// CHECK-INST: st1q {za5v.q[w14, 0]}, p5, [x10, x21, lsl #4]
// CHECK-ENCODING: [0x45,0xd5,0xf5,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 f5 e1 <unknown>
-st1q za7v.q[w15], p3, [x13, x8, lsl #4]
-// CHECK-INST: st1q {za7v.q[w15]}, p3, [x13, x8, lsl #4]
+st1q za7v.q[w15, 0], p3, [x13, x8, lsl #4]
+// CHECK-INST: st1q {za7v.q[w15, 0]}, p3, [x13, x8, lsl #4]
// CHECK-ENCODING: [0xa7,0xed,0xe8,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed e8 e1 <unknown>
-st1q za15v.q[w15], p7, [sp]
-// CHECK-INST: st1q {za15v.q[w15]}, p7, [sp]
+st1q za15v.q[w15, 0], p7, [sp]
+// CHECK-INST: st1q {za15v.q[w15, 0]}, p7, [sp]
// CHECK-ENCODING: [0xef,0xff,0xff,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff ff e1 <unknown>
-st1q za5v.q[w12], p3, [x17, x16, lsl #4]
-// CHECK-INST: st1q {za5v.q[w12]}, p3, [x17, x16, lsl #4]
+st1q za5v.q[w12, 0], p3, [x17, x16, lsl #4]
+// CHECK-INST: st1q {za5v.q[w12, 0]}, p3, [x17, x16, lsl #4]
// CHECK-ENCODING: [0x25,0x8e,0xf0,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e f0 e1 <unknown>
-st1q za1v.q[w12], p1, [x1, x30, lsl #4]
-// CHECK-INST: st1q {za1v.q[w12]}, p1, [x1, x30, lsl #4]
+st1q za1v.q[w12, 0], p1, [x1, x30, lsl #4]
+// CHECK-INST: st1q {za1v.q[w12, 0]}, p1, [x1, x30, lsl #4]
// CHECK-ENCODING: [0x21,0x84,0xfe,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 fe e1 <unknown>
-st1q za8v.q[w14], p5, [x19, x20, lsl #4]
-// CHECK-INST: st1q {za8v.q[w14]}, p5, [x19, x20, lsl #4]
+st1q za8v.q[w14, 0], p5, [x19, x20, lsl #4]
+// CHECK-INST: st1q {za8v.q[w14, 0]}, p5, [x19, x20, lsl #4]
// CHECK-ENCODING: [0x68,0xd6,0xf4,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 f4 e1 <unknown>
-st1q za0v.q[w12], p6, [x12, x2, lsl #4]
-// CHECK-INST: st1q {za0v.q[w12]}, p6, [x12, x2, lsl #4]
+st1q za0v.q[w12, 0], p6, [x12, x2, lsl #4]
+// CHECK-INST: st1q {za0v.q[w12, 0]}, p6, [x12, x2, lsl #4]
// CHECK-ENCODING: [0x80,0x99,0xe2,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 e2 e1 <unknown>
-st1q za1v.q[w14], p2, [x1, x26, lsl #4]
-// CHECK-INST: st1q {za1v.q[w14]}, p2, [x1, x26, lsl #4]
+st1q za1v.q[w14, 0], p2, [x1, x26, lsl #4]
+// CHECK-INST: st1q {za1v.q[w14, 0]}, p2, [x1, x26, lsl #4]
// CHECK-ENCODING: [0x21,0xc8,0xfa,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 fa e1 <unknown>
-st1q za13v.q[w12], p2, [x22, x30, lsl #4]
-// CHECK-INST: st1q {za13v.q[w12]}, p2, [x22, x30, lsl #4]
+st1q za13v.q[w12, 0], p2, [x22, x30, lsl #4]
+// CHECK-INST: st1q {za13v.q[w12, 0]}, p2, [x22, x30, lsl #4]
// CHECK-ENCODING: [0xcd,0x8a,0xfe,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a fe e1 <unknown>
-st1q za2v.q[w15], p5, [x9, x1, lsl #4]
-// CHECK-INST: st1q {za2v.q[w15]}, p5, [x9, x1, lsl #4]
+st1q za2v.q[w15, 0], p5, [x9, x1, lsl #4]
+// CHECK-INST: st1q {za2v.q[w15, 0]}, p5, [x9, x1, lsl #4]
// CHECK-ENCODING: [0x22,0xf5,0xe1,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 e1 e1 <unknown>
-st1q za7v.q[w13], p2, [x12, x11, lsl #4]
-// CHECK-INST: st1q {za7v.q[w13]}, p2, [x12, x11, lsl #4]
+st1q za7v.q[w13, 0], p2, [x12, x11, lsl #4]
+// CHECK-INST: st1q {za7v.q[w13, 0]}, p2, [x12, x11, lsl #4]
// CHECK-ENCODING: [0x87,0xa9,0xeb,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 eb e1 <unknown>
diff --git a/llvm/test/MC/AArch64/SME/st1w-diagnostics.s b/llvm/test/MC/AArch64/SME/st1w-diagnostics.s
index 932c918368af2..4edca02855504 100644
--- a/llvm/test/MC/AArch64/SME/st1w-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/st1w-diagnostics.s
@@ -3,32 +3,32 @@
// ------------------------------------------------------------------------- //
// Invalid tile (expected: za[0-3]h.s or za[0-3]v.s)
-st1w {za4h.s[w12, #0]}, p0, [x0]
+st1w {za4h.s[w12, 0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
-// CHECK-NEXT: st1w {za4h.s[w12, #0]}, p0, [x0]
+// CHECK-NEXT: st1w {za4h.s[w12, 0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1w {za[w12, #0]}, p0/z, [x0]
+st1w {za[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3]h.s or za[0-3]v.s
-// CHECK-NEXT: st1w {za[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: st1w {za[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1w {za1v.h[w12, #0]}, p0/z, [x0]
+st1w {za1v.h[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3]h.s or za[0-3]v.s
-// CHECK-NEXT: st1w {za1v.h[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: st1w {za1v.h[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid vector select register (expected: w12-w15)
-st1w {za0h.s[w11, #0]}, p0, [x0]
+st1w {za0h.s[w11, 0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: st1w {za0h.s[w11, #0]}, p0, [x0]
+// CHECK-NEXT: st1w {za0h.s[w11, 0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1w {za0h.s[w16, #0]}, p0, [x0]
+st1w {za0h.s[w16, 0]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: st1w {za0h.s[w16, #0]}, p0, [x0]
+// CHECK-NEXT: st1w {za0h.s[w16, 0]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
@@ -39,46 +39,46 @@ st1w {za0h.s[w12]}, p0, [x0]
// CHECK-NEXT: st1w {za0h.s[w12]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1w {za0h.s[w12, #4]}, p0, [x0]
+st1w {za0h.s[w12, 4]}, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3].
-// CHECK-NEXT: st1w {za0h.s[w12, #4]}, p0, [x0]
+// CHECK-NEXT: st1w {za0h.s[w12, 4]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate (expected: p0-p7)
-st1w {za0h.s[w12, #0]}, p8, [x0]
+st1w {za0h.s[w12, 0]}, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
-// CHECK-NEXT: st1w {za0h.s[w12, #0]}, p8, [x0]
+// CHECK-NEXT: st1w {za0h.s[w12, 0]}, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Unexpected predicate qualifier
-st1w {za0h.s[w12, #0]}, p0/z, [x0]
+st1w {za0h.s[w12, 0]}, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: st1w {za0h.s[w12, #0]}, p0/z, [x0]
+// CHECK-NEXT: st1w {za0h.s[w12, 0]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1w {za0h.s[w12, #0]}, p0/m, [x0]
+st1w {za0h.s[w12, 0]}, p0/m, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: st1w {za0h.s[w12, #0]}, p0/m, [x0]
+// CHECK-NEXT: st1w {za0h.s[w12, 0]}, p0/m, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid memory operands
-st1w {za0h.s[w12, #0]}, p0, [w0]
+st1w {za0h.s[w12, 0]}, p0, [w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: st1w {za0h.s[w12, #0]}, p0, [w0]
+// CHECK-NEXT: st1w {za0h.s[w12, 0]}, p0, [w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1w {za0h.s[w12, #0]}, p0, [x0, w0]
+st1w {za0h.s[w12, 0]}, p0, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
-// CHECK-NEXT: st1w {za0h.s[w12, #0]}, p0, [x0, w0]
+// CHECK-NEXT: st1w {za0h.s[w12, 0]}, p0, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-st1w {za0h.s[w12, #0]}, p0, [x0, x0, lsl #3]
+st1w {za0h.s[w12, 0]}, p0, [x0, x0, lsl #3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
-// CHECK-NEXT: st1w {za0h.s[w12, #0]}, p0, [x0, x0, lsl #3]
+// CHECK-NEXT: st1w {za0h.s[w12, 0]}, p0, [x0, x0, lsl #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/st1w.s b/llvm/test/MC/AArch64/SME/st1w.s
index ef0d68e58e8bf..70254f132defa 100644
--- a/llvm/test/MC/AArch64/SME/st1w.s
+++ b/llvm/test/MC/AArch64/SME/st1w.s
@@ -15,146 +15,146 @@
// --------------------------------------------------------------------------//
// Horizontal
-st1w {za0h.s[w12, #0]}, p0, [x0, x0, lsl #2]
-// CHECK-INST: st1w {za0h.s[w12, #0]}, p0, [x0, x0, lsl #2]
+st1w {za0h.s[w12, 0]}, p0, [x0, x0, lsl #2]
+// CHECK-INST: st1w {za0h.s[w12, 0]}, p0, [x0, x0, lsl #2]
// CHECK-ENCODING: [0x00,0x00,0xa0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 a0 e0 <unknown>
-st1w {za1h.s[w14, #1]}, p5, [x10, x21, lsl #2]
-// CHECK-INST: st1w {za1h.s[w14, #1]}, p5, [x10, x21, lsl #2]
+st1w {za1h.s[w14, 1]}, p5, [x10, x21, lsl #2]
+// CHECK-INST: st1w {za1h.s[w14, 1]}, p5, [x10, x21, lsl #2]
// CHECK-ENCODING: [0x45,0x55,0xb5,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 b5 e0 <unknown>
-st1w {za1h.s[w15, #3]}, p3, [x13, x8, lsl #2]
-// CHECK-INST: st1w {za1h.s[w15, #3]}, p3, [x13, x8, lsl #2]
+st1w {za1h.s[w15, 3]}, p3, [x13, x8, lsl #2]
+// CHECK-INST: st1w {za1h.s[w15, 3]}, p3, [x13, x8, lsl #2]
// CHECK-ENCODING: [0xa7,0x6d,0xa8,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d a8 e0 <unknown>
-st1w {za3h.s[w15, #3]}, p7, [sp]
-// CHECK-INST: st1w {za3h.s[w15, #3]}, p7, [sp]
+st1w {za3h.s[w15, 3]}, p7, [sp]
+// CHECK-INST: st1w {za3h.s[w15, 3]}, p7, [sp]
// CHECK-ENCODING: [0xef,0x7f,0xbf,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f bf e0 <unknown>
-st1w {za1h.s[w12, #1]}, p3, [x17, x16, lsl #2]
-// CHECK-INST: st1w {za1h.s[w12, #1]}, p3, [x17, x16, lsl #2]
+st1w {za1h.s[w12, 1]}, p3, [x17, x16, lsl #2]
+// CHECK-INST: st1w {za1h.s[w12, 1]}, p3, [x17, x16, lsl #2]
// CHECK-ENCODING: [0x25,0x0e,0xb0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e b0 e0 <unknown>
-st1w {za0h.s[w12, #1]}, p1, [x1, x30, lsl #2]
-// CHECK-INST: st1w {za0h.s[w12, #1]}, p1, [x1, x30, lsl #2]
+st1w {za0h.s[w12, 1]}, p1, [x1, x30, lsl #2]
+// CHECK-INST: st1w {za0h.s[w12, 1]}, p1, [x1, x30, lsl #2]
// CHECK-ENCODING: [0x21,0x04,0xbe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 be e0 <unknown>
-st1w {za2h.s[w14, #0]}, p5, [x19, x20, lsl #2]
-// CHECK-INST: st1w {za2h.s[w14, #0]}, p5, [x19, x20, lsl #2]
+st1w {za2h.s[w14, 0]}, p5, [x19, x20, lsl #2]
+// CHECK-INST: st1w {za2h.s[w14, 0]}, p5, [x19, x20, lsl #2]
// CHECK-ENCODING: [0x68,0x56,0xb4,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 b4 e0 <unknown>
-st1w {za0h.s[w12, #0]}, p6, [x12, x2, lsl #2]
-// CHECK-INST: st1w {za0h.s[w12, #0]}, p6, [x12, x2, lsl #2]
+st1w {za0h.s[w12, 0]}, p6, [x12, x2, lsl #2]
+// CHECK-INST: st1w {za0h.s[w12, 0]}, p6, [x12, x2, lsl #2]
// CHECK-ENCODING: [0x80,0x19,0xa2,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 a2 e0 <unknown>
-st1w {za0h.s[w14, #1]}, p2, [x1, x26, lsl #2]
-// CHECK-INST: st1w {za0h.s[w14, #1]}, p2, [x1, x26, lsl #2]
+st1w {za0h.s[w14, 1]}, p2, [x1, x26, lsl #2]
+// CHECK-INST: st1w {za0h.s[w14, 1]}, p2, [x1, x26, lsl #2]
// CHECK-ENCODING: [0x21,0x48,0xba,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 ba e0 <unknown>
-st1w {za3h.s[w12, #1]}, p2, [x22, x30, lsl #2]
-// CHECK-INST: st1w {za3h.s[w12, #1]}, p2, [x22, x30, lsl #2]
+st1w {za3h.s[w12, 1]}, p2, [x22, x30, lsl #2]
+// CHECK-INST: st1w {za3h.s[w12, 1]}, p2, [x22, x30, lsl #2]
// CHECK-ENCODING: [0xcd,0x0a,0xbe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a be e0 <unknown>
-st1w {za0h.s[w15, #2]}, p5, [x9, x1, lsl #2]
-// CHECK-INST: st1w {za0h.s[w15, #2]}, p5, [x9, x1, lsl #2]
+st1w {za0h.s[w15, 2]}, p5, [x9, x1, lsl #2]
+// CHECK-INST: st1w {za0h.s[w15, 2]}, p5, [x9, x1, lsl #2]
// CHECK-ENCODING: [0x22,0x75,0xa1,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 a1 e0 <unknown>
-st1w {za1h.s[w13, #3]}, p2, [x12, x11, lsl #2]
-// CHECK-INST: st1w {za1h.s[w13, #3]}, p2, [x12, x11, lsl #2]
+st1w {za1h.s[w13, 3]}, p2, [x12, x11, lsl #2]
+// CHECK-INST: st1w {za1h.s[w13, 3]}, p2, [x12, x11, lsl #2]
// CHECK-ENCODING: [0x87,0x29,0xab,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 ab e0 <unknown>
-st1w za0h.s[w12, #0], p0, [x0, x0, lsl #2]
-// CHECK-INST: st1w {za0h.s[w12, #0]}, p0, [x0, x0, lsl #2]
+st1w za0h.s[w12, 0], p0, [x0, x0, lsl #2]
+// CHECK-INST: st1w {za0h.s[w12, 0]}, p0, [x0, x0, lsl #2]
// CHECK-ENCODING: [0x00,0x00,0xa0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 a0 e0 <unknown>
-st1w za1h.s[w14, #1], p5, [x10, x21, lsl #2]
-// CHECK-INST: st1w {za1h.s[w14, #1]}, p5, [x10, x21, lsl #2]
+st1w za1h.s[w14, 1], p5, [x10, x21, lsl #2]
+// CHECK-INST: st1w {za1h.s[w14, 1]}, p5, [x10, x21, lsl #2]
// CHECK-ENCODING: [0x45,0x55,0xb5,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 b5 e0 <unknown>
-st1w za1h.s[w15, #3], p3, [x13, x8, lsl #2]
-// CHECK-INST: st1w {za1h.s[w15, #3]}, p3, [x13, x8, lsl #2]
+st1w za1h.s[w15, 3], p3, [x13, x8, lsl #2]
+// CHECK-INST: st1w {za1h.s[w15, 3]}, p3, [x13, x8, lsl #2]
// CHECK-ENCODING: [0xa7,0x6d,0xa8,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d a8 e0 <unknown>
-st1w za3h.s[w15, #3], p7, [sp]
-// CHECK-INST: st1w {za3h.s[w15, #3]}, p7, [sp]
+st1w za3h.s[w15, 3], p7, [sp]
+// CHECK-INST: st1w {za3h.s[w15, 3]}, p7, [sp]
// CHECK-ENCODING: [0xef,0x7f,0xbf,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7f bf e0 <unknown>
-st1w za1h.s[w12, #1], p3, [x17, x16, lsl #2]
-// CHECK-INST: st1w {za1h.s[w12, #1]}, p3, [x17, x16, lsl #2]
+st1w za1h.s[w12, 1], p3, [x17, x16, lsl #2]
+// CHECK-INST: st1w {za1h.s[w12, 1]}, p3, [x17, x16, lsl #2]
// CHECK-ENCODING: [0x25,0x0e,0xb0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 0e b0 e0 <unknown>
-st1w za0h.s[w12, #1], p1, [x1, x30, lsl #2]
-// CHECK-INST: st1w {za0h.s[w12, #1]}, p1, [x1, x30, lsl #2]
+st1w za0h.s[w12, 1], p1, [x1, x30, lsl #2]
+// CHECK-INST: st1w {za0h.s[w12, 1]}, p1, [x1, x30, lsl #2]
// CHECK-ENCODING: [0x21,0x04,0xbe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 04 be e0 <unknown>
-st1w za2h.s[w14, #0], p5, [x19, x20, lsl #2]
-// CHECK-INST: st1w {za2h.s[w14, #0]}, p5, [x19, x20, lsl #2]
+st1w za2h.s[w14, 0], p5, [x19, x20, lsl #2]
+// CHECK-INST: st1w {za2h.s[w14, 0]}, p5, [x19, x20, lsl #2]
// CHECK-ENCODING: [0x68,0x56,0xb4,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 56 b4 e0 <unknown>
-st1w za0h.s[w12, #0], p6, [x12, x2, lsl #2]
-// CHECK-INST: st1w {za0h.s[w12, #0]}, p6, [x12, x2, lsl #2]
+st1w za0h.s[w12, 0], p6, [x12, x2, lsl #2]
+// CHECK-INST: st1w {za0h.s[w12, 0]}, p6, [x12, x2, lsl #2]
// CHECK-ENCODING: [0x80,0x19,0xa2,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 19 a2 e0 <unknown>
-st1w za0h.s[w14, #1], p2, [x1, x26, lsl #2]
-// CHECK-INST: st1w {za0h.s[w14, #1]}, p2, [x1, x26, lsl #2]
+st1w za0h.s[w14, 1], p2, [x1, x26, lsl #2]
+// CHECK-INST: st1w {za0h.s[w14, 1]}, p2, [x1, x26, lsl #2]
// CHECK-ENCODING: [0x21,0x48,0xba,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 48 ba e0 <unknown>
-st1w za3h.s[w12, #1], p2, [x22, x30, lsl #2]
-// CHECK-INST: st1w {za3h.s[w12, #1]}, p2, [x22, x30, lsl #2]
+st1w za3h.s[w12, 1], p2, [x22, x30, lsl #2]
+// CHECK-INST: st1w {za3h.s[w12, 1]}, p2, [x22, x30, lsl #2]
// CHECK-ENCODING: [0xcd,0x0a,0xbe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 0a be e0 <unknown>
-st1w za0h.s[w15, #2], p5, [x9, x1, lsl #2]
-// CHECK-INST: st1w {za0h.s[w15, #2]}, p5, [x9, x1, lsl #2]
+st1w za0h.s[w15, 2], p5, [x9, x1, lsl #2]
+// CHECK-INST: st1w {za0h.s[w15, 2]}, p5, [x9, x1, lsl #2]
// CHECK-ENCODING: [0x22,0x75,0xa1,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 75 a1 e0 <unknown>
-st1w za1h.s[w13, #3], p2, [x12, x11, lsl #2]
-// CHECK-INST: st1w {za1h.s[w13, #3]}, p2, [x12, x11, lsl #2]
+st1w za1h.s[w13, 3], p2, [x12, x11, lsl #2]
+// CHECK-INST: st1w {za1h.s[w13, 3]}, p2, [x12, x11, lsl #2]
// CHECK-ENCODING: [0x87,0x29,0xab,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 29 ab e0 <unknown>
@@ -162,146 +162,146 @@ st1w za1h.s[w13, #3], p2, [x12, x11, lsl #2]
// --------------------------------------------------------------------------//
// Vertical
-st1w {za0v.s[w12, #0]}, p0, [x0, x0, lsl #2]
-// CHECK-INST: st1w {za0v.s[w12, #0]}, p0, [x0, x0, lsl #2]
+st1w {za0v.s[w12, 0]}, p0, [x0, x0, lsl #2]
+// CHECK-INST: st1w {za0v.s[w12, 0]}, p0, [x0, x0, lsl #2]
// CHECK-ENCODING: [0x00,0x80,0xa0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 a0 e0 <unknown>
-st1w {za1v.s[w14, #1]}, p5, [x10, x21, lsl #2]
-// CHECK-INST: st1w {za1v.s[w14, #1]}, p5, [x10, x21, lsl #2]
+st1w {za1v.s[w14, 1]}, p5, [x10, x21, lsl #2]
+// CHECK-INST: st1w {za1v.s[w14, 1]}, p5, [x10, x21, lsl #2]
// CHECK-ENCODING: [0x45,0xd5,0xb5,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 b5 e0 <unknown>
-st1w {za1v.s[w15, #3]}, p3, [x13, x8, lsl #2]
-// CHECK-INST: st1w {za1v.s[w15, #3]}, p3, [x13, x8, lsl #2]
+st1w {za1v.s[w15, 3]}, p3, [x13, x8, lsl #2]
+// CHECK-INST: st1w {za1v.s[w15, 3]}, p3, [x13, x8, lsl #2]
// CHECK-ENCODING: [0xa7,0xed,0xa8,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed a8 e0 <unknown>
-st1w {za3v.s[w15, #3]}, p7, [sp]
-// CHECK-INST: st1w {za3v.s[w15, #3]}, p7, [sp]
+st1w {za3v.s[w15, 3]}, p7, [sp]
+// CHECK-INST: st1w {za3v.s[w15, 3]}, p7, [sp]
// CHECK-ENCODING: [0xef,0xff,0xbf,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff bf e0 <unknown>
-st1w {za1v.s[w12, #1]}, p3, [x17, x16, lsl #2]
-// CHECK-INST: st1w {za1v.s[w12, #1]}, p3, [x17, x16, lsl #2]
+st1w {za1v.s[w12, 1]}, p3, [x17, x16, lsl #2]
+// CHECK-INST: st1w {za1v.s[w12, 1]}, p3, [x17, x16, lsl #2]
// CHECK-ENCODING: [0x25,0x8e,0xb0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e b0 e0 <unknown>
-st1w {za0v.s[w12, #1]}, p1, [x1, x30, lsl #2]
-// CHECK-INST: st1w {za0v.s[w12, #1]}, p1, [x1, x30, lsl #2]
+st1w {za0v.s[w12, 1]}, p1, [x1, x30, lsl #2]
+// CHECK-INST: st1w {za0v.s[w12, 1]}, p1, [x1, x30, lsl #2]
// CHECK-ENCODING: [0x21,0x84,0xbe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 be e0 <unknown>
-st1w {za2v.s[w14, #0]}, p5, [x19, x20, lsl #2]
-// CHECK-INST: st1w {za2v.s[w14, #0]}, p5, [x19, x20, lsl #2]
+st1w {za2v.s[w14, 0]}, p5, [x19, x20, lsl #2]
+// CHECK-INST: st1w {za2v.s[w14, 0]}, p5, [x19, x20, lsl #2]
// CHECK-ENCODING: [0x68,0xd6,0xb4,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 b4 e0 <unknown>
-st1w {za0v.s[w12, #0]}, p6, [x12, x2, lsl #2]
-// CHECK-INST: st1w {za0v.s[w12, #0]}, p6, [x12, x2, lsl #2]
+st1w {za0v.s[w12, 0]}, p6, [x12, x2, lsl #2]
+// CHECK-INST: st1w {za0v.s[w12, 0]}, p6, [x12, x2, lsl #2]
// CHECK-ENCODING: [0x80,0x99,0xa2,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 a2 e0 <unknown>
-st1w {za0v.s[w14, #1]}, p2, [x1, x26, lsl #2]
-// CHECK-INST: st1w {za0v.s[w14, #1]}, p2, [x1, x26, lsl #2]
+st1w {za0v.s[w14, 1]}, p2, [x1, x26, lsl #2]
+// CHECK-INST: st1w {za0v.s[w14, 1]}, p2, [x1, x26, lsl #2]
// CHECK-ENCODING: [0x21,0xc8,0xba,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 ba e0 <unknown>
-st1w {za3v.s[w12, #1]}, p2, [x22, x30, lsl #2]
-// CHECK-INST: st1w {za3v.s[w12, #1]}, p2, [x22, x30, lsl #2]
+st1w {za3v.s[w12, 1]}, p2, [x22, x30, lsl #2]
+// CHECK-INST: st1w {za3v.s[w12, 1]}, p2, [x22, x30, lsl #2]
// CHECK-ENCODING: [0xcd,0x8a,0xbe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a be e0 <unknown>
-st1w {za0v.s[w15, #2]}, p5, [x9, x1, lsl #2]
-// CHECK-INST: st1w {za0v.s[w15, #2]}, p5, [x9, x1, lsl #2]
+st1w {za0v.s[w15, 2]}, p5, [x9, x1, lsl #2]
+// CHECK-INST: st1w {za0v.s[w15, 2]}, p5, [x9, x1, lsl #2]
// CHECK-ENCODING: [0x22,0xf5,0xa1,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 a1 e0 <unknown>
-st1w {za1v.s[w13, #3]}, p2, [x12, x11, lsl #2]
-// CHECK-INST: st1w {za1v.s[w13, #3]}, p2, [x12, x11, lsl #2]
+st1w {za1v.s[w13, 3]}, p2, [x12, x11, lsl #2]
+// CHECK-INST: st1w {za1v.s[w13, 3]}, p2, [x12, x11, lsl #2]
// CHECK-ENCODING: [0x87,0xa9,0xab,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 ab e0 <unknown>
-st1w za0v.s[w12, #0], p0, [x0, x0, lsl #2]
-// CHECK-INST: st1w {za0v.s[w12, #0]}, p0, [x0, x0, lsl #2]
+st1w za0v.s[w12, 0], p0, [x0, x0, lsl #2]
+// CHECK-INST: st1w {za0v.s[w12, 0]}, p0, [x0, x0, lsl #2]
// CHECK-ENCODING: [0x00,0x80,0xa0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 80 a0 e0 <unknown>
-st1w za1v.s[w14, #1], p5, [x10, x21, lsl #2]
-// CHECK-INST: st1w {za1v.s[w14, #1]}, p5, [x10, x21, lsl #2]
+st1w za1v.s[w14, 1], p5, [x10, x21, lsl #2]
+// CHECK-INST: st1w {za1v.s[w14, 1]}, p5, [x10, x21, lsl #2]
// CHECK-ENCODING: [0x45,0xd5,0xb5,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 d5 b5 e0 <unknown>
-st1w za1v.s[w15, #3], p3, [x13, x8, lsl #2]
-// CHECK-INST: st1w {za1v.s[w15, #3]}, p3, [x13, x8, lsl #2]
+st1w za1v.s[w15, 3], p3, [x13, x8, lsl #2]
+// CHECK-INST: st1w {za1v.s[w15, 3]}, p3, [x13, x8, lsl #2]
// CHECK-ENCODING: [0xa7,0xed,0xa8,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 ed a8 e0 <unknown>
-st1w za3v.s[w15, #3], p7, [sp]
-// CHECK-INST: st1w {za3v.s[w15, #3]}, p7, [sp]
+st1w za3v.s[w15, 3], p7, [sp]
+// CHECK-INST: st1w {za3v.s[w15, 3]}, p7, [sp]
// CHECK-ENCODING: [0xef,0xff,0xbf,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef ff bf e0 <unknown>
-st1w za1v.s[w12, #1], p3, [x17, x16, lsl #2]
-// CHECK-INST: st1w {za1v.s[w12, #1]}, p3, [x17, x16, lsl #2]
+st1w za1v.s[w12, 1], p3, [x17, x16, lsl #2]
+// CHECK-INST: st1w {za1v.s[w12, 1]}, p3, [x17, x16, lsl #2]
// CHECK-ENCODING: [0x25,0x8e,0xb0,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 8e b0 e0 <unknown>
-st1w za0v.s[w12, #1], p1, [x1, x30, lsl #2]
-// CHECK-INST: st1w {za0v.s[w12, #1]}, p1, [x1, x30, lsl #2]
+st1w za0v.s[w12, 1], p1, [x1, x30, lsl #2]
+// CHECK-INST: st1w {za0v.s[w12, 1]}, p1, [x1, x30, lsl #2]
// CHECK-ENCODING: [0x21,0x84,0xbe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 84 be e0 <unknown>
-st1w za2v.s[w14, #0], p5, [x19, x20, lsl #2]
-// CHECK-INST: st1w {za2v.s[w14, #0]}, p5, [x19, x20, lsl #2]
+st1w za2v.s[w14, 0], p5, [x19, x20, lsl #2]
+// CHECK-INST: st1w {za2v.s[w14, 0]}, p5, [x19, x20, lsl #2]
// CHECK-ENCODING: [0x68,0xd6,0xb4,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 d6 b4 e0 <unknown>
-st1w za0v.s[w12, #0], p6, [x12, x2, lsl #2]
-// CHECK-INST: st1w {za0v.s[w12, #0]}, p6, [x12, x2, lsl #2]
+st1w za0v.s[w12, 0], p6, [x12, x2, lsl #2]
+// CHECK-INST: st1w {za0v.s[w12, 0]}, p6, [x12, x2, lsl #2]
// CHECK-ENCODING: [0x80,0x99,0xa2,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 99 a2 e0 <unknown>
-st1w za0v.s[w14, #1], p2, [x1, x26, lsl #2]
-// CHECK-INST: st1w {za0v.s[w14, #1]}, p2, [x1, x26, lsl #2]
+st1w za0v.s[w14, 1], p2, [x1, x26, lsl #2]
+// CHECK-INST: st1w {za0v.s[w14, 1]}, p2, [x1, x26, lsl #2]
// CHECK-ENCODING: [0x21,0xc8,0xba,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 c8 ba e0 <unknown>
-st1w za3v.s[w12, #1], p2, [x22, x30, lsl #2]
-// CHECK-INST: st1w {za3v.s[w12, #1]}, p2, [x22, x30, lsl #2]
+st1w za3v.s[w12, 1], p2, [x22, x30, lsl #2]
+// CHECK-INST: st1w {za3v.s[w12, 1]}, p2, [x22, x30, lsl #2]
// CHECK-ENCODING: [0xcd,0x8a,0xbe,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 8a be e0 <unknown>
-st1w za0v.s[w15, #2], p5, [x9, x1, lsl #2]
-// CHECK-INST: st1w {za0v.s[w15, #2]}, p5, [x9, x1, lsl #2]
+st1w za0v.s[w15, 2], p5, [x9, x1, lsl #2]
+// CHECK-INST: st1w {za0v.s[w15, 2]}, p5, [x9, x1, lsl #2]
// CHECK-ENCODING: [0x22,0xf5,0xa1,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 f5 a1 e0 <unknown>
-st1w za1v.s[w13, #3], p2, [x12, x11, lsl #2]
-// CHECK-INST: st1w {za1v.s[w13, #3]}, p2, [x12, x11, lsl #2]
+st1w za1v.s[w13, 3], p2, [x12, x11, lsl #2]
+// CHECK-INST: st1w {za1v.s[w13, 3]}, p2, [x12, x11, lsl #2]
// CHECK-ENCODING: [0x87,0xa9,0xab,0xe0]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 a9 ab e0 <unknown>
diff --git a/llvm/test/MC/AArch64/SME/str.s b/llvm/test/MC/AArch64/SME/str.s
index 1079678c585a2..202dc8e4be0d9 100644
--- a/llvm/test/MC/AArch64/SME/str.s
+++ b/llvm/test/MC/AArch64/SME/str.s
@@ -12,74 +12,74 @@
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-str za[w12, #0], [x0]
-// CHECK-INST: str za[w12, #0], [x0]
+str za[w12, 0], [x0]
+// CHECK-INST: str za[w12, 0], [x0]
// CHECK-ENCODING: [0x00,0x00,0x20,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 00 20 e1 <unknown>
-str za[w14, #5], [x10, #5, mul vl]
-// CHECK-INST: str za[w14, #5], [x10, #5, mul vl]
+str za[w14, 5], [x10, #5, mul vl]
+// CHECK-INST: str za[w14, 5], [x10, #5, mul vl]
// CHECK-ENCODING: [0x45,0x41,0x20,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 41 20 e1 <unknown>
-str za[w15, #7], [x13, #7, mul vl]
-// CHECK-INST: str za[w15, #7], [x13, #7, mul vl]
+str za[w15, 7], [x13, #7, mul vl]
+// CHECK-INST: str za[w15, 7], [x13, #7, mul vl]
// CHECK-ENCODING: [0xa7,0x61,0x20,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 61 20 e1 <unknown>
-str za[w15, #15], [sp, #15, mul vl]
-// CHECK-INST: str za[w15, #15], [sp, #15, mul vl]
+str za[w15, 15], [sp, #15, mul vl]
+// CHECK-INST: str za[w15, 15], [sp, #15, mul vl]
// CHECK-ENCODING: [0xef,0x63,0x20,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 63 20 e1 <unknown>
-str za[w12, #5], [x17, #5, mul vl]
-// CHECK-INST: str za[w12, #5], [x17, #5, mul vl]
+str za[w12, 5], [x17, #5, mul vl]
+// CHECK-INST: str za[w12, 5], [x17, #5, mul vl]
// CHECK-ENCODING: [0x25,0x02,0x20,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 25 02 20 e1 <unknown>
-str za[w12, #1], [x1, #1, mul vl]
-// CHECK-INST: str za[w12, #1], [x1, #1, mul vl]
+str za[w12, 1], [x1, #1, mul vl]
+// CHECK-INST: str za[w12, 1], [x1, #1, mul vl]
// CHECK-ENCODING: [0x21,0x00,0x20,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 00 20 e1 <unknown>
-str za[w14, #8], [x19, #8, mul vl]
-// CHECK-INST: str za[w14, #8], [x19, #8, mul vl]
+str za[w14, 8], [x19, #8, mul vl]
+// CHECK-INST: str za[w14, 8], [x19, #8, mul vl]
// CHECK-ENCODING: [0x68,0x42,0x20,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 68 42 20 e1 <unknown>
-str za[w12, #0], [x12]
-// CHECK-INST: str za[w12, #0], [x12]
+str za[w12, 0], [x12]
+// CHECK-INST: str za[w12, 0], [x12]
// CHECK-ENCODING: [0x80,0x01,0x20,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 80 01 20 e1 <unknown>
-str za[w14, #1], [x1, #1, mul vl]
-// CHECK-INST: str za[w14, #1], [x1, #1, mul vl]
+str za[w14, 1], [x1, #1, mul vl]
+// CHECK-INST: str za[w14, 1], [x1, #1, mul vl]
// CHECK-ENCODING: [0x21,0x40,0x20,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 21 40 20 e1 <unknown>
-str za[w12, #13], [x22, #13, mul vl]
-// CHECK-INST: str za[w12, #13], [x22, #13, mul vl]
+str za[w12, 13], [x22, #13, mul vl]
+// CHECK-INST: str za[w12, 13], [x22, #13, mul vl]
// CHECK-ENCODING: [0xcd,0x02,0x20,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: cd 02 20 e1 <unknown>
-str za[w15, #2], [x9, #2, mul vl]
-// CHECK-INST: str za[w15, #2], [x9, #2, mul vl]
+str za[w15, 2], [x9, #2, mul vl]
+// CHECK-INST: str za[w15, 2], [x9, #2, mul vl]
// CHECK-ENCODING: [0x22,0x61,0x20,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 22 61 20 e1 <unknown>
-str za[w13, #7], [x12, #7, mul vl]
-// CHECK-INST: str za[w13, #7], [x12, #7, mul vl]
+str za[w13, 7], [x12, #7, mul vl]
+// CHECK-INST: str za[w13, 7], [x12, #7, mul vl]
// CHECK-ENCODING: [0x87,0x21,0x20,0xe1]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 87 21 20 e1 <unknown>
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