[llvm] 14cb138 - [AArch64][SME] Update DUP (predicate) instruction
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 7 01:55:44 PDT 2021
Author: Cullen Rhodes
Date: 2021-10-07T08:55:11Z
New Revision: 14cb138b15adafe7d4a1cd7cb2e836c40a5957b5
URL: https://github.com/llvm/llvm-project/commit/14cb138b15adafe7d4a1cd7cb2e836c40a5957b5
DIFF: https://github.com/llvm/llvm-project/commit/14cb138b15adafe7d4a1cd7cb2e836c40a5957b5.diff
LOG: [AArch64][SME] Update DUP (predicate) instruction
Changes in architecture revision 00eac1:
* Renamed to PSEL.
* Copies whole source register.
* Element type suffix removed from destination.
* Element index no longer optional and '#' prefix has been removed.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-09
Depends on D111212.
Reviewed By: kmclaughlin
Differential Revision: https://reviews.llvm.org/D111213
Added:
llvm/test/MC/AArch64/SME/psel-diagnostics.s
llvm/test/MC/AArch64/SME/psel.s
Modified:
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
llvm/lib/Target/AArch64/SMEInstrFormats.td
Removed:
llvm/test/MC/AArch64/SME/dup-diagnostics.s
llvm/test/MC/AArch64/SME/dup.s
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index 6a0fa2fc4f4e0..aacace64e9983 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -138,6 +138,6 @@ def REVD_ZPmZ : sve2_int_perm_revd<"revd">;
defm SCLAMP_ZZZ : sve2_clamp<"sclamp", 0b0>;
defm UCLAMP_ZZZ : sve2_clamp<"uclamp", 0b1>;
-defm DUP_PPzPRI : sve2_int_perm_dup_p<"dup">;
+defm PSEL_PPPRI : sve2_int_perm_sel_p<"psel">;
} // End let Predicates = [HasSME]
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index 6b339cbbb66e7..41f2cead4cf8d 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -679,57 +679,48 @@ multiclass sve2_clamp<string asm, bit U> {
def _D : sve2_clamp<asm, 0b11, U, ZPR64>;
}
-class sve2_int_perm_dup_p<string asm, PPRRegOp ppr_ty, Operand imm_ty>
- : I<(outs ppr_ty:$Pd), (ins PPRAny:$Pg, ppr_ty:$Pn,
- MatrixIndexGPR32Op12_15:$Rm, imm_ty:$imm),
- asm, "\t$Pd, $Pg/z, $Pn[$Rm, $imm]", "", []>,
+class sve2_int_perm_sel_p<string asm, PPRRegOp ppr_ty, Operand imm_ty>
+ : I<(outs PPRAny:$Pd), (ins PPRAny:$Pn, ppr_ty:$Pm,
+ MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm),
+ asm, "\t$Pd, $Pn, $Pm[$Rv, $imm]", "", []>,
Sched<[]> {
- bits<2> Rm;
- bits<4> Pg;
+ bits<2> Rv;
bits<4> Pn;
+ bits<4> Pm;
bits<4> Pd;
let Inst{31-24} = 0b00100101;
let Inst{21} = 0b1;
- let Inst{17-16} = Rm;
+ let Inst{17-16} = Rv;
let Inst{15-14} = 0b01;
- let Inst{13-10} = Pg;
+ let Inst{13-10} = Pn;
let Inst{9} = 0b0;
- let Inst{8-5} = Pn;
+ let Inst{8-5} = Pm;
let Inst{4} = 0b0;
let Inst{3-0} = Pd;
}
-multiclass sve2_int_perm_dup_p<string asm> {
- def _B : sve2_int_perm_dup_p<asm, PPR8, imm0_15> {
+multiclass sve2_int_perm_sel_p<string asm> {
+ def _B : sve2_int_perm_sel_p<asm, PPR8, sme_elm_idx0_15> {
bits<4> imm;
let Inst{23-22} = imm{3-2};
let Inst{20-19} = imm{1-0};
let Inst{18} = 0b1;
}
- def _H : sve2_int_perm_dup_p<asm, PPR16, imm0_7> {
+ def _H : sve2_int_perm_sel_p<asm, PPR16, sme_elm_idx0_7> {
bits<3> imm;
let Inst{23-22} = imm{2-1};
let Inst{20} = imm{0};
let Inst{19-18} = 0b10;
}
- def _S : sve2_int_perm_dup_p<asm, PPR32, imm0_3> {
+ def _S : sve2_int_perm_sel_p<asm, PPR32, sme_elm_idx0_3> {
bits<2> imm;
let Inst{23-22} = imm{1-0};
let Inst{20-18} = 0b100;
}
- def _D : sve2_int_perm_dup_p<asm, PPR64, imm0_1> {
+ def _D : sve2_int_perm_sel_p<asm, PPR64, sme_elm_idx0_1> {
bits<1> imm;
let Inst{23} = imm;
let Inst{22} = 0b1;
let Inst{20-18} = 0b000;
}
-
- def : InstAlias<"dup\t$Pd, $Pg/z, $Pn[$Rm]",
- (!cast<Instruction>(NAME # _B) PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, MatrixIndexGPR32Op12_15:$Rm, 0), 1>;
- def : InstAlias<"dup\t$Pd, $Pg/z, $Pn[$Rm]",
- (!cast<Instruction>(NAME # _H) PPR16:$Pd, PPRAny:$Pg, PPR16:$Pn, MatrixIndexGPR32Op12_15:$Rm, 0), 1>;
- def : InstAlias<"dup\t$Pd, $Pg/z, $Pn[$Rm]",
- (!cast<Instruction>(NAME # _S) PPR32:$Pd, PPRAny:$Pg, PPR32:$Pn, MatrixIndexGPR32Op12_15:$Rm, 0), 1>;
- def : InstAlias<"dup\t$Pd, $Pg/z, $Pn[$Rm]",
- (!cast<Instruction>(NAME # _D) PPR64:$Pd, PPRAny:$Pg, PPR64:$Pn, MatrixIndexGPR32Op12_15:$Rm, 0), 1>;
}
diff --git a/llvm/test/MC/AArch64/SME/dup-diagnostics.s b/llvm/test/MC/AArch64/SME/psel-diagnostics.s
similarity index 58%
rename from llvm/test/MC/AArch64/SME/dup-diagnostics.s
rename to llvm/test/MC/AArch64/SME/psel-diagnostics.s
index 6321f43970742..70eb6bd1df338 100644
--- a/llvm/test/MC/AArch64/SME/dup-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/psel-diagnostics.s
@@ -3,56 +3,44 @@
// ------------------------------------------------------------------------- //
// Invalid predicate
-// wrong predication qualifier, expected /z.
-dup p0.b, p0/m, p0.b[w12]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: dup p0.b, p0/m, p0.b[w12]
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-// mismatched element type
-dup p0.b, p0/z, p0.h[w12]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
-// CHECK-NEXT: dup p0.b, p0/z, p0.h[w12]
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
// missing element type suffix
-dup p0.b, p0/z, p0[w12]
+psel p0, p0, p0[w12]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
-// CHECK-NEXT: dup p0.b, p0/z, p0[w12]
+// CHECK-NEXT: psel p0, p0, p0[w12]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid index base register register (w12-w15)
-dup p0.b, p0/z, p0.b[w11]
+psel p0, p0, p0.b[w11]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: dup p0.b, p0/z, p0.b[w11]
+// CHECK-NEXT: psel p0, p0, p0.b[w11]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-dup p0.b, p0/z, p0.b[w16]
+psel p0, p0, p0.b[w16]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
-// CHECK-NEXT: dup p0.b, p0/z, p0.b[w16]
+// CHECK-NEXT: psel p0, p0, p0.b[w16]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid immediates
-dup p0.b, p0/z, p0.b[w12, #16]
+psel p0, p0, p0.b[w12, #16]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
-// CHECK-NEXT: dup p0.b, p0/z, p0.b[w12, #16]
+// CHECK-NEXT: psel p0, p0, p0.b[w12, #16]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-dup p0.h, p0/z, p0.h[w12, #8]
+psel p0, p0, p0.h[w12, #8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
-// CHECK-NEXT: dup p0.h, p0/z, p0.h[w12, #8]
+// CHECK-NEXT: psel p0, p0, p0.h[w12, #8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-dup p0.s, p0/z, p0.s[w12, #4]
+psel p0, p0, p0.s[w12, #4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3].
-// CHECK-NEXT: dup p0.s, p0/z, p0.s[w12, #4]
+// CHECK-NEXT: psel p0, p0, p0.s[w12, #4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-dup p0.d, p0/z, p0.d[w12, #2]
+psel p0, p0, p0.d[w12, #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
-// CHECK-NEXT: dup p0.d, p0/z, p0.d[w12, #2]
+// CHECK-NEXT: psel p0, p0, p0.d[w12, #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/dup.s b/llvm/test/MC/AArch64/SME/psel.s
similarity index 71%
rename from llvm/test/MC/AArch64/SME/dup.s
rename to llvm/test/MC/AArch64/SME/psel.s
index 07d71701f75f4..70be719ccf579 100644
--- a/llvm/test/MC/AArch64/SME/dup.s
+++ b/llvm/test/MC/AArch64/SME/psel.s
@@ -15,26 +15,26 @@
// --------------------------------------------------------------------------//
// 8-bit
-dup p0.b, p0/z, p0.b[w12]
-// CHECK-INST: dup p0.b, p0/z, p0.b[w12]
+psel p0, p0, p0.b[w12, 0]
+// CHECK-INST: psel p0, p0, p0.b[w12, 0]
// CHECK-ENCODING: [0x00,0x40,0x24,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 40 24 25 <unknown>
-dup p5.b, p5/z, p10.b[w13, #6]
-// CHECK-INST: dup p5.b, p5/z, p10.b[w13, #6]
+psel p5, p5, p10.b[w13, 6]
+// CHECK-INST: psel p5, p5, p10.b[w13, 6]
// CHECK-ENCODING: [0x45,0x55,0x75,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 75 25 <unknown>
-dup p7.b, p11/z, p13.b[w12, #5]
-// CHECK-INST: dup p7.b, p11/z, p13.b[w12, #5]
+psel p7, p11, p13.b[w12, 5]
+// CHECK-INST: psel p7, p11, p13.b[w12, 5]
// CHECK-ENCODING: [0xa7,0x6d,0x6c,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 6c 25 <unknown>
-dup p15.b, p15/z, p15.b[w15, #15]
-// CHECK-INST: dup p15.b, p15/z, p15.b[w15, #15]
+psel p15, p15, p15.b[w15, 15]
+// CHECK-INST: psel p15, p15, p15.b[w15, 15]
// CHECK-ENCODING: [0xef,0x7d,0xff,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7d ff 25 <unknown>
@@ -42,26 +42,26 @@ dup p15.b, p15/z, p15.b[w15, #15]
// --------------------------------------------------------------------------//
// 16-bit
-dup p0.h, p0/z, p0.h[w12]
-// CHECK-INST: dup p0.h, p0/z, p0.h[w12]
+psel p0, p0, p0.h[w12, 0]
+// CHECK-INST: psel p0, p0, p0.h[w12, 0]
// CHECK-ENCODING: [0x00,0x40,0x28,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 40 28 25 <unknown>
-dup p5.h, p5/z, p10.h[w13, #3]
-// CHECK-INST: dup p5.h, p5/z, p10.h[w13, #3]
+psel p5, p5, p10.h[w13, 3]
+// CHECK-INST: psel p5, p5, p10.h[w13, 3]
// CHECK-ENCODING: [0x45,0x55,0x79,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 79 25 <unknown>
-dup p7.h, p11/z, p13.h[w12, #2]
-// CHECK-INST: dup p7.h, p11/z, p13.h[w12, #2]
+psel p7, p11, p13.h[w12, 2]
+// CHECK-INST: psel p7, p11, p13.h[w12, 2]
// CHECK-ENCODING: [0xa7,0x6d,0x68,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 68 25 <unknown>
-dup p15.h, p15/z, p15.h[w15, #7]
-// CHECK-INST: dup p15.h, p15/z, p15.h[w15, #7]
+psel p15, p15, p15.h[w15, 7]
+// CHECK-INST: psel p15, p15, p15.h[w15, 7]
// CHECK-ENCODING: [0xef,0x7d,0xfb,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7d fb 25 <unknown>
@@ -69,26 +69,26 @@ dup p15.h, p15/z, p15.h[w15, #7]
// --------------------------------------------------------------------------//
// 32-bit
-dup p0.s, p0/z, p0.s[w12]
-// CHECK-INST: dup p0.s, p0/z, p0.s[w12]
+psel p0, p0, p0.s[w12, 0]
+// CHECK-INST: psel p0, p0, p0.s[w12, 0]
// CHECK-ENCODING: [0x00,0x40,0x30,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 40 30 25 <unknown>
-dup p5.s, p5/z, p10.s[w13, #1]
-// CHECK-INST: dup p5.s, p5/z, p10.s[w13, #1]
+psel p5, p5, p10.s[w13, 1]
+// CHECK-INST: psel p5, p5, p10.s[w13, 1]
// CHECK-ENCODING: [0x45,0x55,0x71,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 71 25 <unknown>
-dup p7.s, p11/z, p13.s[w12, #1]
-// CHECK-INST: dup p7.s, p11/z, p13.s[w12, #1]
+psel p7, p11, p13.s[w12, 1]
+// CHECK-INST: psel p7, p11, p13.s[w12, 1]
// CHECK-ENCODING: [0xa7,0x6d,0x70,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 70 25 <unknown>
-dup p15.s, p15/z, p15.s[w15, #3]
-// CHECK-INST: dup p15.s, p15/z, p15.s[w15, #3]
+psel p15, p15, p15.s[w15, 3]
+// CHECK-INST: psel p15, p15, p15.s[w15, 3]
// CHECK-ENCODING: [0xef,0x7d,0xf3,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7d f3 25 <unknown>
@@ -96,26 +96,26 @@ dup p15.s, p15/z, p15.s[w15, #3]
// --------------------------------------------------------------------------//
// 64-bit
-dup p0.d, p0/z, p0.d[w12]
-// CHECK-INST: dup p0.d, p0/z, p0.d[w12]
+psel p0, p0, p0.d[w12, 0]
+// CHECK-INST: psel p0, p0, p0.d[w12, 0]
// CHECK-ENCODING: [0x00,0x40,0x60,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 00 40 60 25 <unknown>
-dup p5.d, p5/z, p10.d[w13]
-// CHECK-INST: dup p5.d, p5/z, p10.d[w13]
+psel p5, p5, p10.d[w13, 0]
+// CHECK-INST: psel p5, p5, p10.d[w13, 0]
// CHECK-ENCODING: [0x45,0x55,0x61,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 45 55 61 25 <unknown>
-dup p7.d, p11/z, p13.d[w12]
-// CHECK-INST: dup p7.d, p11/z, p13.d[w12]
+psel p7, p11, p13.d[w12, 0]
+// CHECK-INST: psel p7, p11, p13.d[w12, 0]
// CHECK-ENCODING: [0xa7,0x6d,0x60,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: a7 6d 60 25 <unknown>
-dup p15.d, p15/z, p15.d[w15, #1]
-// CHECK-INST: dup p15.d, p15/z, p15.d[w15, #1]
+psel p15, p15, p15.d[w15, 1]
+// CHECK-INST: psel p15, p15, p15.d[w15, 1]
// CHECK-ENCODING: [0xef,0x7d,0xe3,0x25]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: ef 7d e3 25 <unknown>
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