[PATCH] D111285: Fix invalid Kill on callee save on RISC-V
David Callahan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 6 19:02:03 PDT 2021
david2050 created this revision.
david2050 added reviewers: tra, lewis-revill, asb.
Herald added subscribers: vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
david2050 requested review of this revision.
Herald added subscribers: llvm-commits, MaskRay.
Herald added a project: LLVM.
A callee save may be live (specifically X1) on entry and so a spill should not mark it killed.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D111285
Files:
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Index: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -1046,7 +1046,7 @@
// Insert the spill to the stack frame.
Register Reg = CS.getReg();
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
- TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);
+ TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg), CS.getFrameIdx(), RC, TRI);
}
return true;
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