[PATCH] D111221: [AArch64][SVE] Improve code generation for VLS i1 masks

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16044
+    if (V && V->isZero())
+      return LHS->getOperand(0);
+  }
----------------
I believe this transform is sound for a normal `SETCC` but `N` is a `SETCC_MERGE_ZERO` and so consideration must be paid to the predicate to ensure the inactive lanes get zero'd.

The easiest way to make the combine safe is to check `Pred` is all active.  The problem with doing that is it'll probably mean the combine doesn't fire for the case you care about.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111221/new/

https://reviews.llvm.org/D111221