[PATCH] D111221: [AArch64][SVE] Improve code generation for VLS i1 masks

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15345
+static SDValue performSunpkloCombine(SDNode *N, SelectionDAG &DAG) {
+  if (N->getOperand(0).getOpcode() == ISD::SIGN_EXTEND &&
+      N->getOperand(0)->getOperand(0)->getValueType(0).getScalarType() ==
----------------
nit. As many of the other combines have, please could you introduce a comment showing the form of the intended combine?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16036
 
+  if (Cond == ISD::SETNE && isZerosVector(RHS.getNode()) &&
+      LHS->getOpcode() == ISD::SIGN_EXTEND &&
----------------
nit. As many of the other combines have, please could you introduce a comment showing the form of the combine?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111221/new/

https://reviews.llvm.org/D111221