[PATCH] D111092: [X86][Costmodel] Load/store i64/f64 Stride=6 VF=2 interleaving costs

Mon Oct 4 12:29:50 PDT 2021

lebedev.ri created this revision.
lebedev.ri added a reviewer: RKSimon.
lebedev.ri added a project: LLVM.
Herald added subscribers: pengfei, hiraditya.
lebedev.ri requested review of this revision.

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/onese7rec - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: =3.0`
So could pick cost of `6`.

For store we have:
https://godbolt.org/z/bMd7dddnT - for intels `Block RThroughput: =8.0`; for ryzens, `Block RThroughput: <=6.0`
So we could pick cost of `8`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111092

Files:
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll


Index: llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
===================================================================

--- llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
@@ -22,7 +22,7 @@
 ; AVX1: LV: Found an estimated cost of 156 for VF 8 For instruction:   store i64 %v5, i64* %out5, align 8
 ;
 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction:   store i64 %v5, i64* %out5, align 8
-; AVX2: LV: Found an estimated cost of 33 for VF 2 For instruction:   store i64 %v5, i64* %out5, align 8
+; AVX2: LV: Found an estimated cost of 11 for VF 2 For instruction:   store i64 %v5, i64* %out5, align 8
 ; AVX2: LV: Found an estimated cost of 78 for VF 4 For instruction:   store i64 %v5, i64* %out5, align 8
 ; AVX2: LV: Found an estimated cost of 156 for VF 8 For instruction:   store i64 %v5, i64* %out5, align 8
 ;
Index: llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
@@ -22,7 +22,7 @@
 ; AVX1: LV: Found an estimated cost of 108 for VF 8 For instruction:   store double %v5, double* %out5, align 8
 ;
 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction:   store double %v5, double* %out5, align 8
-; AVX2: LV: Found an estimated cost of 21 for VF 2 For instruction:   store double %v5, double* %out5, align 8
+; AVX2: LV: Found an estimated cost of 11 for VF 2 For instruction:   store double %v5, double* %out5, align 8
 ; AVX2: LV: Found an estimated cost of 54 for VF 4 For instruction:   store double %v5, double* %out5, align 8
 ; AVX2: LV: Found an estimated cost of 108 for VF 8 For instruction:   store double %v5, double* %out5, align 8
 ;
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
@@ -22,7 +22,7 @@
 ; AVX1: LV: Found an estimated cost of 156 for VF 8 For instruction:   %v0 = load i64, i64* %in0, align 8
 ;
 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load i64, i64* %in0, align 8
-; AVX2: LV: Found an estimated cost of 33 for VF 2 For instruction:   %v0 = load i64, i64* %in0, align 8
+; AVX2: LV: Found an estimated cost of 9 for VF 2 For instruction:   %v0 = load i64, i64* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 78 for VF 4 For instruction:   %v0 = load i64, i64* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 156 for VF 8 For instruction:   %v0 = load i64, i64* %in0, align 8
 ;
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
@@ -22,7 +22,7 @@
 ; AVX1: LV: Found an estimated cost of 96 for VF 8 For instruction:   %v0 = load double, double* %in0, align 8
 ;
 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load double, double* %in0, align 8
-; AVX2: LV: Found an estimated cost of 21 for VF 2 For instruction:   %v0 = load double, double* %in0, align 8
+; AVX2: LV: Found an estimated cost of 9 for VF 2 For instruction:   %v0 = load double, double* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 48 for VF 4 For instruction:   %v0 = load double, double* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 96 for VF 8 For instruction:   %v0 = load double, double* %in0, align 8
 ;
Index: llvm/lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -5139,6 +5139,8 @@
       {6, MVT::v8i16, 39}, // (load 48i16 and) deinterleave into 6 x 8i16
       {6, MVT::v16i16, 106}, // (load 96i16 and) deinterleave into 6 x 16i16
 
+      {6, MVT::v2i64, 6}, // (load 12i64 and) deinterleave into 6 x 2i64
+
       {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32
   };
 
@@ -5210,6 +5212,8 @@
       {6, MVT::v4i16, 15},  // interleave 6 x 4i16 into 24i16 (and store)
       {6, MVT::v8i16, 21},  // interleave 6 x 8i16 into 48i16 (and store)
       {6, MVT::v16i16, 58},  // interleave 6 x 16i16 into 96i16 (and store)
+
+      {6, MVT::v2i64, 8},  // interleave 6 x 2i64 into 12i64 (and store)
   };
 
   if (Opcode == Instruction::Load) {


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