[PATCH] D111060: [X86][Costmodel] Load/store i32/f32 Stride=4 VF=2 interleaving costs

Mon Oct 4 08:04:38 PDT 2021

lebedev.ri created this revision.
lebedev.ri added a reviewer: RKSimon.
lebedev.ri added a project: LLVM.
Herald added subscribers: mstorsjo, pengfei, hiraditya.
lebedev.ri requested review of this revision.

Finally, we are getting to the heavy-hitter stuff!

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/7crGWoar6 - for intels `Block RThroughput: =4.0`; for ryzens, `Block RThroughput: <=2.0`
So could pick cost of `4`.

For store we have:
https://godbolt.org/z/T8aq3MszM - for intels `Block RThroughput: =5.0`; for ryzens, `Block RThroughput: <=2.0`
So we could pick cost of `5`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111060

Files:
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll


Index: llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll
===================================================================

--- llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll
@@ -24,7 +24,7 @@
 ; AVX1: LV: Found an estimated cost of 184 for VF 16 For instruction:   store i32 %v3, i32* %out3, align 4
 ;
 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction:   store i32 %v3, i32* %out3, align 4
-; AVX2: LV: Found an estimated cost of 19 for VF 2 For instruction:   store i32 %v3, i32* %out3, align 4
+; AVX2: LV: Found an estimated cost of 6 for VF 2 For instruction:   store i32 %v3, i32* %out3, align 4
 ; AVX2: LV: Found an estimated cost of 38 for VF 4 For instruction:   store i32 %v3, i32* %out3, align 4
 ; AVX2: LV: Found an estimated cost of 92 for VF 8 For instruction:   store i32 %v3, i32* %out3, align 4
 ; AVX2: LV: Found an estimated cost of 184 for VF 16 For instruction:   store i32 %v3, i32* %out3, align 4
Index: llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-4.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-4.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-4.ll
@@ -24,7 +24,7 @@
 ; AVX1: LV: Found an estimated cost of 152 for VF 16 For instruction:   store float %v3, float* %out3, align 4
 ;
 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction:   store float %v3, float* %out3, align 4
-; AVX2: LV: Found an estimated cost of 13 for VF 2 For instruction:   store float %v3, float* %out3, align 4
+; AVX2: LV: Found an estimated cost of 6 for VF 2 For instruction:   store float %v3, float* %out3, align 4
 ; AVX2: LV: Found an estimated cost of 30 for VF 4 For instruction:   store float %v3, float* %out3, align 4
 ; AVX2: LV: Found an estimated cost of 76 for VF 8 For instruction:   store float %v3, float* %out3, align 4
 ; AVX2: LV: Found an estimated cost of 152 for VF 16 For instruction:   store float %v3, float* %out3, align 4
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll
@@ -24,7 +24,7 @@
 ; AVX1: LV: Found an estimated cost of 184 for VF 16 For instruction:   %v0 = load i32, i32* %in0, align 4
 ;
 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load i32, i32* %in0, align 4
-; AVX2: LV: Found an estimated cost of 21 for VF 2 For instruction:   %v0 = load i32, i32* %in0, align 4
+; AVX2: LV: Found an estimated cost of 5 for VF 2 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 42 for VF 4 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 92 for VF 8 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 184 for VF 16 For instruction:   %v0 = load i32, i32* %in0, align 4
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll
@@ -24,7 +24,7 @@
 ; AVX1: LV: Found an estimated cost of 152 for VF 16 For instruction:   %v0 = load float, float* %in0, align 4
 ;
 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load float, float* %in0, align 4
-; AVX2: LV: Found an estimated cost of 15 for VF 2 For instruction:   %v0 = load float, float* %in0, align 4
+; AVX2: LV: Found an estimated cost of 5 for VF 2 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 34 for VF 4 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 76 for VF 8 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 152 for VF 16 For instruction:   %v0 = load float, float* %in0, align 4
Index: llvm/lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -5128,6 +5128,8 @@
       {4, MVT::v16i16, 75}, // (load 64i16 and) deinterleave into 4 x 16i16
       {4, MVT::v32i16, 150}, // (load 128i16 and) deinterleave into 4 x 32i16
 
+      {4, MVT::v2i32, 4}, // (load 8i32 and) deinterleave into 4 x 2i32
+
       {6, MVT::v2i8, 6}, // (load 12i8 and) deinterleave into 6 x 2i8
       {6, MVT::v4i8, 14}, // (load 24i8 and) deinterleave into 6 x 4i8
       {6, MVT::v8i8, 18}, // (load 48i8 and) deinterleave into 6 x 8i8
@@ -5200,6 +5202,8 @@
       {4, MVT::v16i16, 32},  // interleave 4 x 16i16 into 64i16 (and store)
       {4, MVT::v32i16, 64},  // interleave 4 x 32i16 into 128i16 (and store)
 
+      {4, MVT::v2i32, 5},  // interleave 4 x 2i32 into 8i32 (and store)
+
       {6, MVT::v2i8, 7},  // interleave 6 x 2i8 into 12i8 (and store)
       {6, MVT::v4i8, 9},  // interleave 6 x 4i8 into 24i8 (and store)
       {6, MVT::v8i8, 16},  // interleave 6 x 8i8 into 48i8 (and store)


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