[PATCH] D111031: [WIP][X86][Costmodel] Load/store i64/f64 Stride=3 VF=16 interleaving costs

Sun Oct 3 11:59:47 PDT 2021

lebedev.ri created this revision.
lebedev.ri added a reviewer: RKSimon.
lebedev.ri added a project: LLVM.
Herald added subscribers: pengfei, hiraditya.
lebedev.ri requested review of this revision.

@RKSimon i'm completely stumped by this one, i think it would be good to model this VF,
but i'm just not sure *what* assembly sequence we'd want to measure here...
Suggestions welcomed!

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we may have:
https://godbolt.org/z/vx9z6E5r7 - for intels `Block RThroughput: <=25.0`; for ryzens, `Block RThroughput: <=22.0`
So could pick cost of `25`.

For store we have:
https://godbolt.org/z/33GMhrsG9 - for intels `Block RThroughput: <=26.0`; for ryzens, `Block RThroughput: <=21.0`
So we could pick cost of `26`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111031

Files:
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll


Index: llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll
===================================================================

--- llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 6 for VF 2 For instruction:   store i64 %v2, i64* %out2, align 8
 ; AVX2: LV: Found an estimated cost of 9 for VF 4 For instruction:   store i64 %v2, i64* %out2, align 8
 ; AVX2: LV: Found an estimated cost of 18 for VF 8 For instruction:   store i64 %v2, i64* %out2, align 8
-; AVX2: LV: Found an estimated cost of 156 for VF 16 For instruction:   store i64 %v2, i64* %out2, align 8
+; AVX2: LV: Found an estimated cost of 38 for VF 16 For instruction:   store i64 %v2, i64* %out2, align 8
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   store i64 %v2, i64* %out2, align 8
 ; AVX512: LV: Found an estimated cost of 4 for VF 2 For instruction:   store i64 %v2, i64* %out2, align 8
Index: llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 6 for VF 2 For instruction:   store double %v2, double* %out2, align 8
 ; AVX2: LV: Found an estimated cost of 9 for VF 4 For instruction:   store double %v2, double* %out2, align 8
 ; AVX2: LV: Found an estimated cost of 18 for VF 8 For instruction:   store double %v2, double* %out2, align 8
-; AVX2: LV: Found an estimated cost of 108 for VF 16 For instruction:   store double %v2, double* %out2, align 8
+; AVX2: LV: Found an estimated cost of 38 for VF 16 For instruction:   store double %v2, double* %out2, align 8
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   store double %v2, double* %out2, align 8
 ; AVX512: LV: Found an estimated cost of 4 for VF 2 For instruction:   store double %v2, double* %out2, align 8
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 3 for VF 2 For instruction:   %v0 = load i64, i64* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 8 for VF 4 For instruction:   %v0 = load i64, i64* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 16 for VF 8 For instruction:   %v0 = load i64, i64* %in0, align 8
-; AVX2: LV: Found an estimated cost of 156 for VF 16 For instruction:   %v0 = load i64, i64* %in0, align 8
+; AVX2: LV: Found an estimated cost of 37 for VF 16 For instruction:   %v0 = load i64, i64* %in0, align 8
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load i64, i64* %in0, align 8
 ; AVX512: LV: Found an estimated cost of 4 for VF 2 For instruction:   %v0 = load i64, i64* %in0, align 8
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 3 for VF 2 For instruction:   %v0 = load double, double* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 8 for VF 4 For instruction:   %v0 = load double, double* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 16 for VF 8 For instruction:   %v0 = load double, double* %in0, align 8
-; AVX2: LV: Found an estimated cost of 96 for VF 16 For instruction:   %v0 = load double, double* %in0, align 8
+; AVX2: LV: Found an estimated cost of 37 for VF 16 For instruction:   %v0 = load double, double* %in0, align 8
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load double, double* %in0, align 8
 ; AVX512: LV: Found an estimated cost of 4 for VF 2 For instruction:   %v0 = load double, double* %in0, align 8
Index: llvm/lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -5097,6 +5097,7 @@
       {3, MVT::v2i64, 1},  // (load 6i64 and) deinterleave into 3 x 2i64
       {3, MVT::v4i64, 5},  // (load 12i64 and) deinterleave into 3 x 4i64
       {3, MVT::v8i64, 10},  // (load 24i64 and) deinterleave into 3 x 8i64
+      {3, MVT::v16i64, 25},  // (load 48i64 and) deinterleave into 3 x 16i64
 
       {4, MVT::v2i8, 4},  // (load 8i8 and) deinterleave into 4 x 2i8
       {4, MVT::v4i8, 4},   // (load 16i8 and) deinterleave into 4 x 4i8
@@ -5151,6 +5152,7 @@
       {3, MVT::v2i64, 4},   // interleave 3 x 2i64 into 6i64 (and store)
       {3, MVT::v4i64, 6},   // interleave 3 x 4i64 into 12i64 (and store)
       {3, MVT::v8i64, 12},   // interleave 3 x 8i64 into 24i64 (and store)
+      {3, MVT::v16i64, 26},   // interleave 3 x 16i64 into 48i64 (and store)
 
       {4, MVT::v2i8, 4},  // interleave 4 x 2i8 into 8i8 (and store)
       {4, MVT::v4i8, 4},   // interleave 4 x 4i8 into 16i8 (and store)


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