[PATCH] D110829: [X86] Copy registers in reverse order in convertToThreeAddress

[Jay Foad via Phabricator via llvm-commits]

foad updated this revision to Diff 376587.
foad added a comment.

Rebase on a test case that I will pre-commit.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110829/new/

https://reviews.llvm.org/D110829

Files:
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/test/CodeGen/X86/twoaddr-mul2.ll


Index: llvm/test/CodeGen/X86/twoaddr-mul2.ll
===================================================================
--- llvm/test/CodeGen/X86/twoaddr-mul2.ll
+++ llvm/test/CodeGen/X86/twoaddr-mul2.ll
@@ -1,16 +1,16 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc -mtriple=x86_64-unknown -mcpu=haswell -stop-after=twoaddressinstruction < %s | FileCheck %s
 
-; FIXME: The killed flag should be on the second COPY from [[COPY]], not the first one.
+; Check that the killed flag is on the second COPY from [[COPY]], not the first one.
 define i32 @test_mul_by_2(i32 %x) {
   ; CHECK-LABEL: name: test_mul_by_2
   ; CHECK: bb.0 (%ir-block.0):
   ; CHECK-NEXT:   liveins: $edi
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY killed $edi
-  ; CHECK-NEXT:   undef %2.sub_32bit:gr64 = COPY killed [[COPY]]
-  ; CHECK-NEXT:   undef %3.sub_32bit:gr64_nosp = COPY [[COPY]]
-  ; CHECK-NEXT:   [[LEA64_32r:%[0-9]+]]:gr32 = LEA64_32r killed %2, 1, killed %3, 0, $noreg
+  ; CHECK-NEXT:   undef %2.sub_32bit:gr64_nosp = COPY [[COPY]]
+  ; CHECK-NEXT:   undef %3.sub_32bit:gr64 = COPY killed [[COPY]]
+  ; CHECK-NEXT:   [[LEA64_32r:%[0-9]+]]:gr32 = LEA64_32r killed %3, 1, killed %2, 0, $noreg
   ; CHECK-NEXT:   $eax = COPY killed [[LEA64_32r]]
   ; CHECK-NEXT:   RET 0, killed $eax
   %mul = mul nsw i32 %x, 2
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86InstrInfo.cpp
+++ llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -1532,13 +1532,6 @@
     else
       Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
 
-    bool isKill;
-    Register SrcReg;
-    MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
-    if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
-                        SrcReg, isKill, ImplicitOp, LV))
-      return nullptr;
-
     const MachineOperand &Src2 = MI.getOperand(2);
     bool isKill2;
     Register SrcReg2;
@@ -1547,6 +1540,13 @@
                         SrcReg2, isKill2, ImplicitOp2, LV))
       return nullptr;
 
+    bool isKill;
+    Register SrcReg;
+    MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
+    if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
+                        SrcReg, isKill, ImplicitOp, LV))
+      return nullptr;
+
     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
     if (ImplicitOp.getReg() != 0)
       MIB.add(ImplicitOp);


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