[PATCH] D110231: [AMDGPU] Add constrained shift pattern matches.

[Abinav Puthan Purayil via Phabricator via llvm-commits]

abinavpp added a comment.

I'm still confused between the generic fold approach and the PatFrags approach.

I think the PatFrags approach makes sense, but I'm a bit worried about the large
scale substitution we have to do in all the generic shift opcode references in
all the Target/AMDGPU .td files.

As @foad mentioned, it will be neater if we do (<shift> a, (and b, <width> - 1))
-> (<shift> a, b) in AMDGPU specific compilation where the target <shift> is
generic so that the other generic shift based pattern match (like the v_lshl_add
pattern match) will work. The problem here is that we'll be violating the
generic shift's semantics and, as @arsenm mentioned, creating custom nodes will
be painful.

Is there a situation where the aforementioned folding can go wrong in the AMDGPU
compilation? Also, is there a pre-isel, global-isel and selection-dag-isel
compatible, AMDGPU specific, tablegen way of generating (<shift> a, (and b,
<width> - 1)) -> (<shift> a, b)?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D110231/new/

https://reviews.llvm.org/D110231