[PATCH] D110624: [SVE] Fix incorrect DAG combines when extracting fixed-width from scalable vectors

[David Sherwood via Phabricator via llvm-commits]

david-arm updated this revision to Diff 375556.
david-arm added a comment.

- Actually upload the correct test. :)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110624/new/

https://reviews.llvm.org/D110624

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll


Index: llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
@@ -0,0 +1,11 @@
+; RUN: not --crash llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+; Extracting a fixed-length vector from an illegal subvector
+
+; CHECK-ERROR: ERROR: Extracting a fixed-length vector from an illegal scalable vector is not yet supported
+define <4 x i32> @extract_v4i32_nxv16i32_12(<vscale x 16 x i32> %arg) {
+  %ext = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv16i32(<vscale x 16 x i32> %arg, i64 12)
+  ret <4 x i32> %ext
+}
+
+declare <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv16i32(<vscale x 16 x i32>, i64)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -20602,7 +20602,7 @@
     // If the concatenated source types match this extract, it's a direct
     // simplification:
     // extract_subvec (concat V1, V2, ...), i --> Vi
-    if (ConcatSrcNumElts == ExtNumElts)
+    if (NVT.isScalableVector() == ConcatSrcVT.isScalableVector() && ConcatSrcNumElts == ExtNumElts)
       return V.getOperand(ConcatOpIdx);
 
     // If the concatenated source vectors are a multiple length of this extract,
@@ -20610,7 +20610,8 @@
     // concat operand. Example:
     //   v2i8 extract_subvec (v16i8 concat (v8i8 X), (v8i8 Y), 14 -->
     //   v2i8 extract_subvec v8i8 Y, 6
-    if (NVT.isFixedLengthVector() && ConcatSrcNumElts % ExtNumElts == 0) {
+    if (NVT.isFixedLengthVector() && ConcatSrcVT.isFixedLengthVector() &&
+        ConcatSrcNumElts % ExtNumElts == 0) {
       SDLoc DL(N);
       unsigned NewExtIdx = ExtIdx - ConcatOpIdx * ConcatSrcNumElts;
       assert(NewExtIdx + ExtNumElts <= ConcatSrcNumElts &&


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