[PATCH] D110624: [SVE] Fix incorrect DAG combines when extracting fixed-width from scalable vectors

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll:6
 
+define <4 x i32> @extract_v4i32_nxv16i32(<vscale x 16 x i32> %arg) {
+; CHECK-LABEL: extract_v4i32_nxv16i32:
----------------
Hi all, my apologies. I just realised I've uploaded the wrong test. I will fix asap!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110624/new/

https://reviews.llvm.org/D110624