[PATCH] D107945: [RISCV] Use RISCV::RVVBitsPerBlock for RGK_ScalableVector in getRegisterBitWidth.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D107945#3026709 <https://reviews.llvm.org/D107945#3026709>, @luke957 wrote:

> May I ask a question, why is RISCV::RVVBitsPerBlock set to 64? Any clue(RFC) to this concept? Thanks.

We map RVV types to scalable vector types in IR like <vscale x 1 x i64>.  Where vscale is a runtime value calculated as (VLEN/RVVBitsPerBlock).

So <vscale x 1 x i64> is ((VLEN/RVVBitsPerBlock) x 1 x 64) bits. Which simplifies to VLEN bits. Any type that simplifies to VLEN bits is an LMUL=1 type. Smaller than VLEN represents a fractional LMUL. Larger would LMUL=2 or 4 or 8.

The value needs to be large enough so that we can support a fractional LMUL of 1/8 for i8 which is required for ELEN=64.  With RVVBitsPerBlock==64 we can use <vscale x 1 x i8>. RVVBitsPerBlock also needs to be divisible by ELEN.

RVVBitsPerBlock is the smallest VLEN we can support. I think we are going to need to select a value of 32 at compile time when targeting Zve32x or Zve32f. This will require all the intrinsic types to map to different LLVM IR types depending on which ELEN we are targeting.


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