[PATCH] D110028: [RISCV] Improve support for forming widening multiplies when one input is a scalar splat.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6198
+    // FIXME: Support implicit sign extension of vmv.v.x?
+    if (ScalarBits < EltBits)
+      return SDValue();
----------------
frasercrmck wrote:
> Is `ScalarBits` not always `XLenVT`? Is this basically a "i64 vector on RV32" check?
Yes it should be XLenVT. So this is an i64 on RV32 check.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110028/new/

https://reviews.llvm.org/D110028