[PATCH] D110028: [RISCV] Improve support for forming widening multiplies when one input is a scalar splat.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.
Herald added a subscriber: achieveartificialintelligence.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6198
+    // FIXME: Support implicit sign extension of vmv.v.x?
+    if (ScalarBits < EltBits)
+      return SDValue();
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Is `ScalarBits` not always `XLenVT`? Is this basically a "i64 vector on RV32" check?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110028/new/

https://reviews.llvm.org/D110028