[PATCH] D109300: [AMDGPU] Make vector superclasses allocatable

Fri Sep 24 02:06:56 PDT 2021

rampitec added a comment.

In D109300#3019936 <https://reviews.llvm.org/D109300#3019936>, @cdevadas wrote:

> In D109300#3018937 <https://reviews.llvm.org/D109300#3018937>, @rampitec wrote:
>
>> Thanks. FoldImmediate() and Global ISel seems to be last issue to me.
>
> The MAIInst uses AVSrc_32 for src0 & src1 operands.
> https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/VOP3PInstructions.td#L378
>
> I am not sure we can do something to prevent GIsel from choosing AV classes here.
> Yes, the w/a in FoldImmediate was done to adjust the register class as per the opcode we choose.

Right, that's the only place where we currently have the freedom to chose either v or a, and it is supposed to be resolved at selection. The need to use AV class here comes from MC support so that asm will be free to use any register.

I believe custom code in regbank select can refine the register class for these 2 operands.

I have to note that we cannot rely on the optimization for correctness, if FildImmediate will not run or succeed we will have broken IR and failure, so it has to be fixed in any case.

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