[PATCH] D110342: [x86] convert logic-of-FP-compares to FP logic-of-vector-compares

[Pengfei Wang via Phabricator via llvm-commits]

pengfei added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:45453
 /// If both input operands of a logic op are being cast from floating point
-/// types, try to convert this into a floating point logic node to avoid
-/// unnecessary moves from SSE to integer registers.
+/// types or FP compares, try to convert this into a floating-point logic node
+/// to avoid unnecessary moves from SSE to integer registers.
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Nit, why use hyphen here but leave space above?


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:45510
+  SDValue Logic = DAG.getNode(N->getOpcode(), DL, BoolVecVT, Setcc0, Setcc1);
+  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Logic, ZeroIndex);
 }
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RKSimon wrote:
> Do we need to check/assert that VT is MVT::i1 ?
I think it's Ok since the logic operands come from setcc directly. Do we need to handle `(logic (zext (setcc ...`?


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  https://reviews.llvm.org/D110342/new/

https://reviews.llvm.org/D110342