[PATCH] D110342: [x86] convert logic-of-FP-compares to FP logic-of-vector-compares

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.
This revision is now accepted and ready to land.

LGTM - cheers

I don't think this patch will cover it, but as a follow up please could you add test coverage for logic containing more than 2 fcmps?



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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:45510
+  SDValue Logic = DAG.getNode(N->getOpcode(), DL, BoolVecVT, Setcc0, Setcc1);
+  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Logic, ZeroIndex);
 }
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Do we need to check/assert that VT is MVT::i1 ?


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  https://reviews.llvm.org/D110342/new/

https://reviews.llvm.org/D110342