[llvm] fbacf5a - [RISCV] Add missing op type OPERAND_UIMM2, OPERAND_UIMM3 and OPERAND_UIMM7 for verifyInstruction

[Jim Lin via llvm-commits]

Author: Jim Lin
Date: 2021-09-23T19:30:46+08:00
New Revision: fbacf5ad385c63c73060369ac11dd535e44a37ce

URL: https://github.com/llvm/llvm-project/commit/fbacf5ad385c63c73060369ac11dd535e44a37ce
DIFF: https://github.com/llvm/llvm-project/commit/fbacf5ad385c63c73060369ac11dd535e44a37ce.diff

LOG: [RISCV] Add missing op type OPERAND_UIMM2, OPERAND_UIMM3 and OPERAND_UIMM7 for verifyInstruction

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D110307

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index f25de1801213..95810388494a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -919,12 +919,21 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
         switch (OpType) {
         default:
           llvm_unreachable("Unexpected operand type");
+        case RISCVOp::OPERAND_UIMM2:
+          Ok = isUInt<2>(Imm);
+          break;
+        case RISCVOp::OPERAND_UIMM3:
+          Ok = isUInt<3>(Imm);
+          break;
         case RISCVOp::OPERAND_UIMM4:
           Ok = isUInt<4>(Imm);
           break;
         case RISCVOp::OPERAND_UIMM5:
           Ok = isUInt<5>(Imm);
           break;
+        case RISCVOp::OPERAND_UIMM7:
+          Ok = isUInt<7>(Imm);
+          break;
         case RISCVOp::OPERAND_UIMM12:
           Ok = isUInt<12>(Imm);
           break;