[llvm] f0a422f - [RISCV] Add fcvt.s.w(u)/fcvt.d.w(u)/fcvt.h.w(u) to hasAllNBitUsers

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-09-22T14:24:26-07:00
New Revision: f0a422f935af877d8d9304eacbfbb6621e9ff643

URL: https://github.com/llvm/llvm-project/commit/f0a422f935af877d8d9304eacbfbb6621e9ff643
DIFF: https://github.com/llvm/llvm-project/commit/f0a422f935af877d8d9304eacbfbb6621e9ff643.diff

LOG: [RISCV] Add fcvt.s.w(u)/fcvt.d.w(u)/fcvt.h.w(u) to hasAllNBitUsers

These instructions only read the lower 32 bits of their input.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/test/CodeGen/RISCV/double-convert.ll
    llvm/test/CodeGen/RISCV/float-convert.ll
    llvm/test/CodeGen/RISCV/half-convert.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index d4d460160b9f1..b1d6113deff03 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1572,6 +1572,12 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const {
     case RISCV::CTZW:
     case RISCV::CPOPW:
     case RISCV::SLLIUW:
+    case RISCV::FCVT_H_W:
+    case RISCV::FCVT_H_WU:
+    case RISCV::FCVT_S_W:
+    case RISCV::FCVT_S_WU:
+    case RISCV::FCVT_D_W:
+    case RISCV::FCVT_D_WU:
       if (Bits < 32)
         return false;
       break;

diff  --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
index 4d020075b7f5b..9c7e39cf39e33 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -634,7 +634,6 @@ define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
 }
 
 ; Make sure we select W version of addi on RV64.
-; FIXME: We should not have an addi and addiw on RV64.
 define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) {
 ; RV32IFD-LABEL: fcvt_d_w_demanded_bits:
 ; RV32IFD:       # %bb.0:
@@ -645,11 +644,9 @@ define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) {
 ;
 ; RV64IFD-LABEL: fcvt_d_w_demanded_bits:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    addiw a2, a0, 1
-; RV64IFD-NEXT:    addi a0, a0, 1
+; RV64IFD-NEXT:    addiw a0, a0, 1
 ; RV64IFD-NEXT:    fcvt.d.w ft0, a0
 ; RV64IFD-NEXT:    fsd ft0, 0(a1)
-; RV64IFD-NEXT:    mv a0, a2
 ; RV64IFD-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = sitofp i32 %3 to double

diff  --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll
index 9d42380f435d6..24ceb656d1611 100644
--- a/llvm/test/CodeGen/RISCV/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert.ll
@@ -521,7 +521,6 @@ define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
 }
 
 ; Make sure we select W version of addi on RV64.
-; FIXME: We should not have an addi and addiw on RV64.
 define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) {
 ; RV32IF-LABEL: fcvt_s_w_demanded_bits:
 ; RV32IF:       # %bb.0:
@@ -532,11 +531,9 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) {
 ;
 ; RV64IF-LABEL: fcvt_s_w_demanded_bits:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    addiw a2, a0, 1
-; RV64IF-NEXT:    addi a0, a0, 1
+; RV64IF-NEXT:    addiw a0, a0, 1
 ; RV64IF-NEXT:    fcvt.s.w ft0, a0
 ; RV64IF-NEXT:    fsw ft0, 0(a1)
-; RV64IF-NEXT:    mv a0, a2
 ; RV64IF-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = sitofp i32 %3 to float

diff  --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
index 8850a552412c0..eddbcffdb1b1b 100644
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -1148,7 +1148,6 @@ define i16 @bitcast_i16_h(half %a) nounwind {
 }
 
 ; Make sure we select W version of addi on RV64.
-; FIXME: We should not have an addi and addiw on RV64.
 define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) {
 ; RV32IZFH-LABEL: fcvt_h_w_demanded_bits:
 ; RV32IZFH:       # %bb.0:
@@ -1166,20 +1165,16 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) {
 ;
 ; RV64IZFH-LABEL: fcvt_h_w_demanded_bits:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    addiw a2, a0, 1
-; RV64IZFH-NEXT:    addi a0, a0, 1
+; RV64IZFH-NEXT:    addiw a0, a0, 1
 ; RV64IZFH-NEXT:    fcvt.h.w ft0, a0
 ; RV64IZFH-NEXT:    fsh ft0, 0(a1)
-; RV64IZFH-NEXT:    mv a0, a2
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits:
 ; RV64IDZFH:       # %bb.0:
-; RV64IDZFH-NEXT:    addiw a2, a0, 1
-; RV64IDZFH-NEXT:    addi a0, a0, 1
+; RV64IDZFH-NEXT:    addiw a0, a0, 1
 ; RV64IDZFH-NEXT:    fcvt.h.w ft0, a0
 ; RV64IDZFH-NEXT:    fsh ft0, 0(a1)
-; RV64IDZFH-NEXT:    mv a0, a2
 ; RV64IDZFH-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = sitofp i32 %3 to half