[llvm] c7e7815 - [RISCV] Add test cases showing failure to use ADDIW before fcvt.s.w/fcvt.d.w/fcvt.h.w. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 22 14:25:00 PDT 2021
Author: Craig Topper
Date: 2021-09-22T14:24:26-07:00
New Revision: c7e78150f733d5be3cae766de3385173e2e245ff
URL: https://github.com/llvm/llvm-project/commit/c7e78150f733d5be3cae766de3385173e2e245ff
DIFF: https://github.com/llvm/llvm-project/commit/c7e78150f733d5be3cae766de3385173e2e245ff.diff
LOG: [RISCV] Add test cases showing failure to use ADDIW before fcvt.s.w/fcvt.d.w/fcvt.h.w. NFC
By not using ADDIW we can cause both an ADDIW and ADDI to be emitted
when the add has multiple users.
These instructions needed be added to the list of instructions that
only use the lower 32 bits of input.
I've also added tests for the wu versions, but I'm having trouble
showing bad codegen from it.
Added:
Modified:
llvm/test/CodeGen/RISCV/double-convert.ll
llvm/test/CodeGen/RISCV/float-convert.ll
llvm/test/CodeGen/RISCV/half-convert.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
index d687185e97c4c..4d020075b7f5b 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -632,3 +632,48 @@ define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
%1 = uitofp i16 %a to double
ret double %1
}
+
+; Make sure we select W version of addi on RV64.
+; FIXME: We should not have an addi and addiw on RV64.
+define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) {
+; RV32IFD-LABEL: fcvt_d_w_demanded_bits:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a0, a0, 1
+; RV32IFD-NEXT: fcvt.d.w ft0, a0
+; RV32IFD-NEXT: fsd ft0, 0(a1)
+; RV32IFD-NEXT: ret
+;
+; RV64IFD-LABEL: fcvt_d_w_demanded_bits:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addiw a2, a0, 1
+; RV64IFD-NEXT: addi a0, a0, 1
+; RV64IFD-NEXT: fcvt.d.w ft0, a0
+; RV64IFD-NEXT: fsd ft0, 0(a1)
+; RV64IFD-NEXT: mv a0, a2
+; RV64IFD-NEXT: ret
+ %3 = add i32 %0, 1
+ %4 = sitofp i32 %3 to double
+ store double %4, double* %1, align 8
+ ret i32 %3
+}
+
+; Make sure we select W version of addi on RV64.
+define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, double* %1) {
+; RV32IFD-LABEL: fcvt_d_wu_demanded_bits:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a0, a0, 1
+; RV32IFD-NEXT: fcvt.d.wu ft0, a0
+; RV32IFD-NEXT: fsd ft0, 0(a1)
+; RV32IFD-NEXT: ret
+;
+; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT: addiw a0, a0, 1
+; RV64IFD-NEXT: fcvt.d.wu ft0, a0
+; RV64IFD-NEXT: fsd ft0, 0(a1)
+; RV64IFD-NEXT: ret
+ %3 = add i32 %0, 1
+ %4 = uitofp i32 %3 to double
+ store double %4, double* %1, align 8
+ ret i32 %3
+}
diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll
index ea75715933cc7..9d42380f435d6 100644
--- a/llvm/test/CodeGen/RISCV/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert.ll
@@ -519,3 +519,48 @@ define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
%1 = uitofp i16 %a to float
ret float %1
}
+
+; Make sure we select W version of addi on RV64.
+; FIXME: We should not have an addi and addiw on RV64.
+define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) {
+; RV32IF-LABEL: fcvt_s_w_demanded_bits:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi a0, a0, 1
+; RV32IF-NEXT: fcvt.s.w ft0, a0
+; RV32IF-NEXT: fsw ft0, 0(a1)
+; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_s_w_demanded_bits:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addiw a2, a0, 1
+; RV64IF-NEXT: addi a0, a0, 1
+; RV64IF-NEXT: fcvt.s.w ft0, a0
+; RV64IF-NEXT: fsw ft0, 0(a1)
+; RV64IF-NEXT: mv a0, a2
+; RV64IF-NEXT: ret
+ %3 = add i32 %0, 1
+ %4 = sitofp i32 %3 to float
+ store float %4, float* %1, align 4
+ ret i32 %3
+}
+
+; Make sure we select W version of addi on RV64.
+define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, float* %1) {
+; RV32IF-LABEL: fcvt_s_wu_demanded_bits:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi a0, a0, 1
+; RV32IF-NEXT: fcvt.s.wu ft0, a0
+; RV32IF-NEXT: fsw ft0, 0(a1)
+; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addiw a0, a0, 1
+; RV64IF-NEXT: fcvt.s.wu ft0, a0
+; RV64IF-NEXT: fsw ft0, 0(a1)
+; RV64IF-NEXT: ret
+ %3 = add i32 %0, 1
+ %4 = uitofp i32 %3 to float
+ store float %4, float* %1, align 4
+ ret i32 %3
+}
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
index fc09c12992f41..8850a552412c0 100644
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -1146,3 +1146,78 @@ define i16 @bitcast_i16_h(half %a) nounwind {
%1 = bitcast half %a to i16
ret i16 %1
}
+
+; Make sure we select W version of addi on RV64.
+; FIXME: We should not have an addi and addiw on RV64.
+define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) {
+; RV32IZFH-LABEL: fcvt_h_w_demanded_bits:
+; RV32IZFH: # %bb.0:
+; RV32IZFH-NEXT: addi a0, a0, 1
+; RV32IZFH-NEXT: fcvt.h.w ft0, a0
+; RV32IZFH-NEXT: fsh ft0, 0(a1)
+; RV32IZFH-NEXT: ret
+;
+; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: addi a0, a0, 1
+; RV32IDZFH-NEXT: fcvt.h.w ft0, a0
+; RV32IDZFH-NEXT: fsh ft0, 0(a1)
+; RV32IDZFH-NEXT: ret
+;
+; RV64IZFH-LABEL: fcvt_h_w_demanded_bits:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: addiw a2, a0, 1
+; RV64IZFH-NEXT: addi a0, a0, 1
+; RV64IZFH-NEXT: fcvt.h.w ft0, a0
+; RV64IZFH-NEXT: fsh ft0, 0(a1)
+; RV64IZFH-NEXT: mv a0, a2
+; RV64IZFH-NEXT: ret
+;
+; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits:
+; RV64IDZFH: # %bb.0:
+; RV64IDZFH-NEXT: addiw a2, a0, 1
+; RV64IDZFH-NEXT: addi a0, a0, 1
+; RV64IDZFH-NEXT: fcvt.h.w ft0, a0
+; RV64IDZFH-NEXT: fsh ft0, 0(a1)
+; RV64IDZFH-NEXT: mv a0, a2
+; RV64IDZFH-NEXT: ret
+ %3 = add i32 %0, 1
+ %4 = sitofp i32 %3 to half
+ store half %4, half* %1, align 2
+ ret i32 %3
+}
+
+; Make sure we select W version of addi on RV64.
+define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) {
+; RV32IZFH-LABEL: fcvt_h_wu_demanded_bits:
+; RV32IZFH: # %bb.0:
+; RV32IZFH-NEXT: addi a0, a0, 1
+; RV32IZFH-NEXT: fcvt.h.wu ft0, a0
+; RV32IZFH-NEXT: fsh ft0, 0(a1)
+; RV32IZFH-NEXT: ret
+;
+; RV32IDZFH-LABEL: fcvt_h_wu_demanded_bits:
+; RV32IDZFH: # %bb.0:
+; RV32IDZFH-NEXT: addi a0, a0, 1
+; RV32IDZFH-NEXT: fcvt.h.wu ft0, a0
+; RV32IDZFH-NEXT: fsh ft0, 0(a1)
+; RV32IDZFH-NEXT: ret
+;
+; RV64IZFH-LABEL: fcvt_h_wu_demanded_bits:
+; RV64IZFH: # %bb.0:
+; RV64IZFH-NEXT: addiw a0, a0, 1
+; RV64IZFH-NEXT: fcvt.h.wu ft0, a0
+; RV64IZFH-NEXT: fsh ft0, 0(a1)
+; RV64IZFH-NEXT: ret
+;
+; RV64IDZFH-LABEL: fcvt_h_wu_demanded_bits:
+; RV64IDZFH: # %bb.0:
+; RV64IDZFH-NEXT: addiw a0, a0, 1
+; RV64IDZFH-NEXT: fcvt.h.wu ft0, a0
+; RV64IDZFH-NEXT: fsh ft0, 0(a1)
+; RV64IDZFH-NEXT: ret
+ %3 = add i32 %0, 1
+ %4 = uitofp i32 %3 to half
+ store half %4, half* %1, align 2
+ ret i32 %3
+}
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