[PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 22 12:51:36 PDT 2021

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craig.topper added a comment.

I see, the script was updated to use CHECK-NEXT. Can you pre-commit re-running the script then apply this patch on top?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110250/new/

https://reviews.llvm.org/D110250

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