[PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 22 09:21:42 PDT 2021

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craig.topper added a comment.

Why do we need updates to tests that don't use segment load/store instructions?


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  https://reviews.llvm.org/D110250/new/

https://reviews.llvm.org/D110250

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